Hamid Savoj
Hamid Savoj
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SIS: A system for sequential circuit synthesis
EM Sentovich, KJ Singh, L Lavagno, C Moon, R Murgai, A Saldanha, ...
22691992
Sequential circuit design using synthesis and optimization
EM Sentovich, KJ Singh, C Moon, H Savoj, RK Brayton, ...
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in …, 1992
6331992
Implicit state enumeration of finite state machines using BDD's
HJ Touati, H Savoj, B Lin, RK Brayton, A Sangiovanni-Vincentelli
1990 IEEE International Conference on Computer-Aided Design. Digest of …, 1990
5341990
Chemical function queries for 3D database search
J Greene, S Kahn, H Savoj, P Sprague, S Teig
Journal of Chemical Information and Computer Sciences 34 (6), 1297-1308, 1994
2451994
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
SXD Tan, CJR Shi, JC Lee
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
1742003
Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
MA Riepe, RM Swanson, TM Burks, L Van Ginneken, KF Vahtra, H Savoj
US Patent 7,103,863, 2006
1522006
The use of observability and external don't cares for the simplification of multi-level networks
H Savoj, RK Brayton
Proceedings of the 27th ACM/IEEE Design Automation Conference, 297-301, 1991
1501991
Extracting local don't cares for network optimization
H Savoj, RK Brayton, HJ Touati
1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991
1391991
SIS: A system for sequential circuit analysis
EM Sentovich
Tech. Report, University of California, 1992
1091992
Method for generating design constraints for modules in a hierarchical integrated circuit design system
TM Burks, MA Riepe, H Savoj, RM Swanson, KE Vahtra, L Van Ginneken
US Patent 6,845,494, 2005
812005
Don't cares in mult-level network optimization
H Savoj
University of California, Berkeley, 1992
741992
Delay optimization of combinational logic circuits by clustering and partial collapsing
HJ Touati, H Savoj, RK Brayton
1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991
681991
Timing optimization in presence of interconnect delays
PV Buch, H Savoj, LPPP Van Ginneken
US Patent 6,553,338, 2003
492003
Observability relations and observability don't cares
H Savoj, RK Brayton
1991 IEEE International Conference on Computer-Aided Design Digest of …, 1991
421991
Improved scripts in MIS-II for logic minimization of combinational circuits
H Savoj
International Workshop on Logic Synthesis,(1991), 1991
411991
Boolean matching in logic synthesis
H Savoj, MJ Silva, RK Brayton, A Sangiovanni-Vincentelli
Proceedings EURO-DAC'92: European Design Automation Conference, 168,169,170 …, 1992
341992
Image manipulation for web content
D Berthelot, M Dixon, R Madhavan, M Mapua, P Mihelich, W Min, H Savoj, ...
US Patent 9,405,734, 2016
322016
LEOPARD: A logical effort-based fanout optimizer for area and delay
P Rezvani, AH Ajami, M Pedram, H Savoj
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
301999
Physical synthesis for ASIC datapath circuits
TT Ye, S Chaudhuri, F Huang, H Savoj, G De Micheli
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002
292002
An efficient linear time algorithm for scan chain optimization and repartitioning
D Berthelot, S Chaudhuri, H Savoj
Proceedings. International Test Conference, 781-787, 2002
272002
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