| 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security S Taneja, VK Rajanna, M Alioto 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 498-500, 2021 | 33 | 2021 |
| In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security S Taneja, VK Rajanna, M Alioto IEEE Journal of Solid-State Circuits 57 (1), 153-166, 2021 | 24 | 2021 |
| SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm VK Rajanna, S Taneja, M Alioto ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 7 | 2021 |
| A variation-tolerant replica-based reference-generation technique for single-ended sensing in wide voltage-range SRAMs VK Rajanna, B Amrutur IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 6 | 2015 |
| Low-swing links with dynamic energy-quality trade-off for error-resilient applications VK Rajanna, M Alioto 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 5 | 2019 |
| Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers KR Viveka, B Amrutur Fifth Asia Symposium on Quality Electronic Design (ASQED 2013), 233-239, 2013 | 5 | 2013 |
| Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks VK Rajanna, HS Raghav, T Wang, M Alioto 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 4 | 2022 |
| Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems KR Viveka, B Amrutur 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 4 | 2014 |
| ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm J Basu, S Taneja, VK Rajanna, T Wang, M Alioto 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications VK Rajanna, M Alioto IEEE Journal of Solid-State Circuits 56 (11), 3533-3543, 2021 | 1 | 2021 |
| Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density P Agarwal, VK Rajanna, TW Da, BCK Tee, M Alioto 2021 Symposium on VLSI Circuits, 1-2, 2021 | 1 | 2021 |
| Method and apparatus for unified dynamic and/or multibit static entropy generation inside embedded memory S Taneja, VK RAJANNA, M Alioto US Patent App. 18/262,479, 2024 | | 2024 |
| Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems KA Ahmed, R Yang, P Salamani, V Rajanna, M Alioto ESSCIRC 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC), 49-52, 2023 | | 2023 |
| Design and Characterization of SRAMs for Ultra Dynamic Voltage Scalable (U-DVS) Systems KR Viveka INDIAN INSTITUTE OF SCIENCE, 2016 | | 2016 |
| Low power pipelined TCAM employing mismatch dependent power allocation technique KR Viveka, A Kawle, B Amrutur 20th International Conference on VLSI Design held jointly with 6th …, 2007 | | 2007 |
| Pressure sensor based tsunami detection system: A laboratory study KR Viveka, S Ramgopal, N Praveen, K Rajanna, MM Nayak SENSORS, 2006 IEEE, 1392-1394, 2006 | | 2006 |
| Prof. Arun Kumar Chaudhury Best Paper Award (Tie between two papers) T Xu, K Chakrabarty, PH Jones, YH Cho, JW Lockwood, KR Viveka, ... | | |
| ES1: Student research preview M Verhelst | | |
Massimo AliotoNational University of SingaporeDirección de correo verificada de ieee.org
