| Shakti-T: A RISC-V processor with light weight security extensions A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan Proceedings of the Hardware and Architectural Support for Security and …, 2017 | 59 | 2017 |
| SHAKTI processors: An open-source hardware initiative N Gala, A Menon, R Bodduna, GS Madhusudan, V Kamakoti 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 57 | 2016 |
| SHAKTI-F: A fault tolerant microprocessor architecture S Gupta, N Gala, GS Madhusudan, V Kamakoti 2015 IEEE 24th Asian Test Symposium (ATS), 163-168, 2015 | 45 | 2015 |
| PERI: A configurable posit enabled RISC-V core S Tiwari, N Gala, C Rebeiro, V Kamakoti ACM Transactions on Architecture and Code Optimization (TACO) 18 (3), 1-26, 2021 | 29 | 2021 |
| A programmable event-driven architecture for evaluating spiking neural networks A Roy, S Venkataramani, N Gala, S Sen, K Veezhinathan, ... 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 26 | 2017 |
| Peri: A posit enabled RISC-V core S Tiwari, N Gala, C Rebeiro, V Kamakoti arXiv preprint arXiv:1908.01466, 2019 | 16 | 2019 |
| ELENA: A Low-Cost Portable Electronic Nose For Alcohol Characterization S Murugan, N Gala 2017 IEEE SENSORS, 2017 | 6 | 2017 |
| Approximate error detection with stochastic checkers N Gala, S Venkataramani, A Raghunathan, V Kamakoti IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 5 | 2017 |
| An accuracy tunable non-Boolean co-processor using coupled nano-oscillators N Gala, S Krithivasan, WY Tsai, X Li, V Narayanan, V Kamakoti ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 1-28, 2017 | 4 | 2017 |
| Reconfiguring an ASIC at runtime D Varadarajan, K Srinivasan, NT Gala US Patent 9,698,779, 2017 | 4 | 2017 |
| ProCA: Progressive configuration aware design methodology for low power stochastic ASICs N Gala, VR Devanathan, K Srinivasan, V Visvanathan, V Kamakoti 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 4 | 2014 |
| Sparsity-aware caches to accelerate deep neural networks V Ganesan, S Sen, P Kumar, N Gala, K Veezhinathan, A Raghunathan 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 85-90, 2020 | 3 | 2020 |
| CAERUS: An effective arbitration and ejection policy for routing in an unidirectional torus N Rathod, S Balachandran, N Gala Proceedings of the 8th international workshop on interconnection network …, 2014 | 3 | 2014 |
| Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling N Gala, VR Devanathan, V Visvanathan, V Gandhi, V Kamakoti Fifth Asia Symposium on Quality Electronic Design (ASQED 2013), 103-112, 2013 | 3 | 2013 |
| ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance V Chauhan, N Gala, V Kamakoti 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 1 | 2016 |
| Best is the enemy of good: Design techniques for low power tunable approximate application specific integrated chips targeting media-based applications N Gala, VR Devanathan, V Visvanathan, V Kamakoti Journal of Low Power Electronics 11 (2), 133-148, 2015 | 1 | 2015 |
| Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V SP Kumar, S Singh, N Gala, A Baum | | 2022 |
| STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection N Gala, S Venkataramani, A Raghunathan, V Kamakotit Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | | 2016 |
Kamakoti VeezhinathanProfessor, Department of Computer Science, IIT MadrasDirección de correo verificada de cse.iitm.ac.in
