| Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ... Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 428 | 2016 |
| A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons J Seo, B Brezzo, Y Liu, BD Parker, SK Esser, RK Montoye, B Rajendran, ... 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 339 | 2011 |
| Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 227 | 2017 |
| Specifications of nanoscale devices and circuits for neuromorphic computational systems B Rajendran, Y Liu, J Seo, K Gopalakrishnan, L Chang, DJ Friedman, ... IEEE Transactions on Electron Devices 60 (1), 246-253, 2012 | 155 | 2012 |
| Scalable and modularized RTL compilation of convolutional neural networks onto FPGA Y Ma, N Suda, Y Cao, J Seo, S Vrudhula 2016 26th International Conference on Field Programmable Logic and …, 2016 | 113 | 2016 |
| Mitigating effects of non-ideal synaptic device characteristics for on-chip learning PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015 | 111 | 2015 |
| Optimizing the convolution operation to accelerate deep neural networks on FPGA Y Ma, Y Cao, S Vrudhula, J Seo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018 | 93 | 2018 |
| XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks X Sun, S Yin, X Peng, R Liu, J Seo, S Yu 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 89 | 2018 |
| XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks S Yin, Z Jiang, JS Seo, M Seok IEEE Journal of Solid-State Circuits 55 (6), 1733-1743, 2020 | 83 | 2020 |
| Fully parallel write/read in resistive synaptic array for accelerating on-chip learning L Gao, IT Wang, PY Chen, S Vrudhula, J Seo, Y Cao, TH Hou, S Yu Nanotechnology 26 (45), 455204, 2015 | 82 | 2015 |
| Large-scale neuromorphic spiking array processors: A quest to mimic the brain CS Thakur, JL Molin, G Cauwenberghs, G Indiveri, K Kumar, N Qiao, ... Frontiers in neuroscience 12, 891, 2018 | 80 | 2018 |
| An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo 2017 27th International Conference on Field Programmable Logic and …, 2017 | 76 | 2017 |
| Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip PY Chen, D Kadetotad, Z Xu, A Mohanty, B Lin, J Ye, S Vrudhula, J Seo, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2015 | 75 | 2015 |
| Reconfigurable and customizable general-purpose circuits for neural networks BV Brezzo, L Chang, SK Esser, DJ Friedman, Y Liu, DS Modha, ... US Patent 8,856,055, 2014 | 67 | 2014 |
| High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS J Seo, R Ho, J Lexau, M Dayringer, D Sylvester, D Blaauw 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 182-183, 2010 | 61 | 2010 |
| Parallel architecture with resistive crosspoint array for dictionary learning acceleration D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 56 | 2015 |
| A 2.5 mw 80 db dr 36 db sndr 22 ms/s logarithmic pipeline adc J Lee, J Kang, S Park, J Seo, J Anders, J Guilherme, MP Flynn IEEE Journal of Solid-State Circuits 44 (10), 2755-2765, 2009 | 51 | 2009 |
| Low-power, adaptive neuromorphic systems: Recent progress and future directions A Basu, J Acharya, T Karnik, H Liu, H Li, JS Seo, C Song IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1), 6-27, 2018 | 50 | 2018 |
| Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1,− 1) weights and (+ 1, 0) neurons X Sun, X Peng, PY Chen, R Liu, J Seo, S Yu 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 574-579, 2018 | 45 | 2018 |
| In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter D Fick, N Liu, Z Foo, M Fojtik, J Seo, D Sylvester, D Blaauw 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 188-189, 2010 | 41 | 2010 |
