| Cim-sim: computation in memory simuiator A BanaGozar, K Vadivel, S Stuijk, H Corporaal, S Wong, MA Lebdeh, J Yu, ... Proceedings of the 22nd International Workshop on Software and Compilers for …, 2019 | 22 | 2019 |
| TC-CIM: Empowering tensor comprehensions for computing-in-memory A Drebes, L Chelini, O Zinenko, A Cohen, H Corporaal, T Grosser, ... 10th International Workshop on Polyhedral Compilation Techniques, 2020 | 21 | 2020 |
| A heuristic based real time task assignment algorithm for heterogeneous multiprocessors M Poongothai, A Rajeswari, V Kanishkan IEICE Electronics Express 11 (3), 20130975-20130975, 2014 | 16 | 2014 |
| TDO-CIM: transparent detection and offloading for computation in-memory K Vadivel, L Chelini, A BanaGozar, G Singh, S Corda, R Jordans, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020 | 14 | 2020 |
| Loop overhead reduction techniques for coarse grained reconfigurable architectures K Vadivel, M Wijtvliet, R Jordans, H Corporaal 2017 Euromicro Conference on Digital System Design (DSD), 14-21, 2017 | 11 | 2017 |
| System Simulation of Memristor Based Computation In Memory Platforms A BanaGozar, K Vadivel, J Multanen, P Jääskeläinen, S Stuijk, ... | 10 | 2020 |
| PET-to-MLIR: A polyhedral front-end for MLIR K Komisarczyk, L Chelini, K Vadivel, R Jordans, H Corporaal 2020 23rd Euromicro Conference on Digital System Design (DSD), 551-556, 2020 | 9 | 2020 |
| Towards efficient code generation for exposed datapath architectures K Vadivel, R Jordans, S Stujik, H Corporaal, P Jääskeläinen, H Kultala Proceedings of the 22nd International Workshop on Software and Compilers for …, 2019 | 8 | 2019 |
| SENECA: Building a fully digital neuromorphic processor, design trade-offs and challenges G Tang, K Vadivel, Y Xu, K Shidqi, P Detterer, S Traferro, M Konijnenburg, ... Frontiers in Neuroscience 17, 1187252, 2023 | 5 | 2023 |
| Saca: System-level analog cim accelerators simulation framework: Accurate simulation of non-ideal components GR Fernando, BG Ali, V Kanishkan, C Henk, D Shidhartha 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022 | 2 | 2022 |
| Energy efficient loop mapping techniques for Coarse-Grained Reconfigurable Architecture K Vadivel Master’s thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, 2017 | 2 | 2017 |
| Saca: System-level analog cim accelerators simulation framework: Architecture and cycle-accurate system-to-device simulator V Kanishkan, GR Fernando, BG Ali, C Henk, D Shidhartha 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022 | 1 | 2022 |
| Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures K Vadivel, B De Bruin, R Jordans, H Corporaal, P Jääskeläinen 2022 25th Euromicro Conference on Digital System Design (DSD), 157-164, 2022 | 1 | 2022 |
| Benchmarking the Epiphany Processor as a Reference Neuromorphic Architecture M Molendijk, K Vadivel, F Corradi, GJ Schaik, A Yousefzadeh, ... Industrial Artificial Intelligence Technologies and Applications, 21-34, 2022 | 1 | 2022 |
| R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA B de Bruin, K Vadivel, M Wijtvliet, P Jääskeläinen, H Corporaal ACM Transactions on Reconfigurable Technology and Systems, 2024 | | 2024 |
| Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration Y Xu, K Shidqi, GJ van Schaik, R Bilgic, A Dobrita, S Wang, R Meijer, ... Frontiers in Neuroscience 18, 1335422, 2024 | | 2024 |
| Additional Reviewers DSD 2019 Y Zhou, M Zhang, B Yin, H Yao, J Wesselkamper, P Weiss, K Vadivel, ... | | |
Henk CorporaalProfessor Embedded System Architectures, Eindhoven University of TechnologyDirección de correo verificada de tue.nl
