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AADIL TAHIR SHORA
AADIL TAHIR SHORA
Scholar, University of Kashmir
Dirección de correo verificada de kashmiruniversity.net
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Analytical modelling and performance analysis of gate-and channel-engineered trapezoidal trigate MOSFET
AT Shora, FA Khanday
IET Circuits, Devices & Systems 13 (8), 1107-1116, 2019
72019
3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET
AT Shora, FA Khanday
Journal of Semiconductors 39 (12), 124016, 2018
52018
Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET
AT Shora, FA Khanday
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2019
42019
Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET
AT Shora, FA Khanday
International Journal of Electronics Letters, 1-15, 2019
22019
Analytical Modelling for nanoscale Gate Engineered Silicon-On-Nothing MOSFET with High-K dielectric
AT Shora, FA Khanday
2018 3rd International Conference on Communication and Electronics Systems …, 2018
22018
Compact Modeling based performance analysis of Trapezoidal Trigate SOI MOSFET
AT Shora, FA Khanday
2018 3rd IEEE International Conference on Recent Trends in Electronics …, 2018
12018
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