| Fully synthesizable PUF featuring hysteresis and temperature compensation for 3.2% native BER and 1.02 fJ/b in 40 nm S Taneja, AB Alvarez, M Alioto IEEE Journal of Solid-State Circuits 53 (10), 2828-2839, 2018 | 84 | 2018 |
| Token-based security for the Internet of Things with dynamic energy-quality tradeoff MN Aman, S Taneja, B Sikdar, KC Chua, M Alioto IEEE Internet of Things Journal 6 (2), 2843-2859, 2018 | 72 | 2018 |
| 36.1 unified in-memory dynamic TRNG and multi-bit static PUF entropy generation for ubiquitous hardware security S Taneja, VK Rajanna, M Alioto 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 498-500, 2021 | 32 | 2021 |
| In-memory unified TRNG and multi-bit PUF for ubiquitous hardware security S Taneja, VK Rajanna, M Alioto IEEE Journal of Solid-State Circuits 57 (1), 153-166, 2021 | 24 | 2021 |
| Enabling ubiquitous hardware security via energy-efficient primitives and systems M Alioto, S Taneja 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2019 | 15 | 2019 |
| Fully synthesizable unified true random number generator and cryptographic core S Taneja, M Alioto IEEE Journal of Solid-State Circuits 56 (10), 3049-3061, 2021 | 13 | 2021 |
| PUF architecture with run-time adaptation for resilient and energy-efficient key generation via sensor fusion S Taneja, M Alioto IEEE Journal of Solid-State Circuits 56 (7), 2182-2192, 2021 | 12 | 2021 |
| A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%–99.99% Error Coverage in Intel 4 CMOS R Kumar, AL Varna, C Tokunaga, S Taneja, V De, SK Mathew IEEE Journal of Solid-State Circuits, 2023 | 8 | 2023 |
| SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm VK Rajanna, S Taneja, M Alioto ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021 | 7 | 2021 |
| Fully synthesizable all-digital unified dynamic entropy generation, extraction, and utilization within the same cryptographic core S Taneja, M Alioto IEEE Solid-State Circuits Letters 3, 402-405, 2020 | 5 | 2020 |
| A 7-Gbps SCA-resistant multiplicative-masked AES engine in Intel 4 CMOS R Kumar, VB Suresh, S Taneja, MA Anders, S Hsu, A Agarwal, V De, ... IEEE Journal of Solid-State Circuits 58 (4), 1106-1116, 2022 | 4 | 2022 |
| Deep sub-pj/bit low-area energy-security scalable simon crypto-core in 40 nm S Taneja, M Alioto 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 4 | 2020 |
| A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02 fJ/b at 0.8–1.0 V in 40nm S Taneja, A Alvarez, G Sadagopan, M Alioto 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 301-304, 2017 | 4 | 2017 |
| HW security primitives database M Alioto, S Taneja http://www.green-ic.org/hwsecdb, 0 | 3* | |
| ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm J Basu, S Taneja, VK Rajanna, T Wang, M Alioto 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm A Gupta, S Kumar, V Konandur, S Taneja, M Alioto 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| PUF-based key generation with design margin reduction via in-situ and PVT sensor fusion S Taneja, M Alioto ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC), 61-64, 2019 | 1 | 2019 |
| Ultra-Low Power Crypto-Engine Based on Simon 32/64 for Energy-and Area-Constrained Integrated Systems S Taneja, M Alioto arXiv preprint arXiv:1811.08507, 2018 | 1 | 2018 |
| A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology V Verma, S Taneja, P Singh, SK Jain 2015 28th IEEE International System-on-Chip Conference (SOCC), 304-309, 2015 | 1 | 2015 |
| Method and apparatus for unified dynamic and/or multibit static entropy generation inside embedded memory S Taneja, VK RAJANNA, M Alioto US Patent App. 18/262,479, 2024 | | 2024 |
Sanu MathewIntel CorporationDirección de correo verificada de intel.com
