Navid Paydavosi

Citado por

	Total	Desde 2019
Citas	1040	509
Índice h	17	11
Índice i10	21	11

120

2010201120122013201420152016201720182019202020212022202320243 10 10 44 58 86 95 107 114 113 89 108 96 81 22

Acceso público

Ver todo

2 artículos

disponibles

no disponibles

Basado en requisitos de financiación

Coautores

Ali M NIKNEJADUC BerkeleyDirección de correo verificada de berkeley.edu
Sriramkumar VenugopalanSemiconductors ProfessionalDirección de correo verificada de eecs.berkeley.edu
chenming huUniversity of California, BerkeleyDirección de correo verificada de eecs.berkeley.edu
Juan Pablo Duarte SepulvedaAppleDirección de correo verificada de apple.com
Yogesh S. ChauhanFellow IEEE, FNAE, Professor-IIT KanpurDirección de correo verificada de iitk.ac.in
sourabh khandelwalUC BerkeleyDirección de correo verificada de berkeley.edu
Jandhyala SrivatsavaSemiconductor Industry, BangaloreDirección de correo verificada de iiit.ac.in
Pragya KushwahaIndian Institute of Technology JodhpurDirección de correo verificada de iitj.ac.in
Muhammed Ahosan Ul KarimElectrical Engineering and Computer Sciences, University of California, BerkeleyDirección de correo verificada de eecs.berkeley.edu
Christian EnzEcole Polytechnique Fédérale de Lausanne (EPFL)Dirección de correo verificada de epfl.ch
Maria-Anna ChalkiadakiInfineon TechnologiesDirección de correo verificada de infineon.com
Christopher RogersSenior Silicon Photonics Engineer, Pointcloud Inc.Dirección de correo verificada de stanford.edu
Neophytos NeophytouSchool of Engineering, University of WarwickDirección de correo verificada de warwick.ac.uk
Meysam ZarghamApple incDirección de correo verificada de mail.utoronto.ca
Angada SachidASM

Seguir

Navid Paydavosi

Device Engineer, Intel

Dirección de correo verificada de intel.com

Semiconductor Physics


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
FinFET modeling for IC simulation and design: using the BSIM-CMG standard YS Chauhan, D Lu, S Vanugopalan, S Khandelwal, JP Duarte, ... Academic Press, 2015	229	2015
BSIM—SPICE models enable FinFET and UTB IC designs N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ... IEEE Access 1, 201-215, 2013	135	2013
BSIM6: Analog and RF compact model for bulk MOSFET YS Chauhan, S Venugopalan, MA Chalkiadaki, MAU Karim, H Agarwal, ... IEEE Transactions on Electron Devices 61 (2), 234-244, 2013	132	2013
BSIM—Industry standard compact MOSFET models YS Chauhan, S Venugopalan, MA Karim, S Khandelwal, N Paydavosi, ... 2012 Proceedings of the European Solid-State Device Research Conference …, 2012	82	2012
Bsim4v4. 8.0 mosfet model N Paydavosi, TH Morshed, DD Lu, WM Yang, MV Dunga, XJ Xi, J He, ... University of California, Berkeley (CA), 2013	41	2013
Unified FinFET compact model: Modelling trapezoidal triple-gate FinFETs JP Duarte, N Paydavosi, S Venugopalan, A Sachid, C Hu 2013 International Conference on Simulation of Semiconductor Processes and …, 2013	40	2013
BSIM compact MOSFET models for SPICE simulation YS Chauhan, S Venugopalan, N Paydavosi, P Kushwaha, S Jandhyala, ... Proceedings of the 20th International Conference Mixed Design of Integrated …, 2013	37	2013
Modeling the impact of substrate depletion in FDSOI MOSFETs P Kushwaha, N Paydavosi, S Khandelwal, C Yadav, H Agarwal, ... Solid-State Electronics 104, 6-11, 2015	32	2015
Recent enhancements in BSIM6 bulk MOSFET model H Agarwal, S Venugopalan, MA Chalkiadaki, N Paydavosi, JP Duarte, ... 2013 International Conference on Simulation of Semiconductor Processes and …, 2013	30	2013
Impact of Contact Resistance on the and of Graphene Versus Transistors KD Holland, AU Alam, N Paydavosi, M Wong, CM Rogers, S Rizwan, ... IEEE Transactions on Nanotechnology 16 (1), 94-106, 2016	26	2016
RF linearity potential of carbon-nanotube transistors versus MOSFETs AU Alam, CMS Rogers, N Paydavosi, KD Holland, S Ahmed, ... IEEE transactions on nanotechnology 12 (3), 340-351, 2013	26	2013
BSIM-CMG 110.0. 0: Multi-gate MOSFET compact model: technical manual S Khandelwal, JP Duarte, AS Medury, S Venugopalan, N Paydavosi, ... BSIM Group UC Berkeley, 2015	25	2015
BSIM6: Symmetric bulk MOSFET model YS Chauhan, MA Karim, S Venugopalan, S Khandelwal, P Thakur, ... Nanotechnology 2012: Electronics, Devices, Fabrication, MEMS, Fluidics and …, 2012	22	2012
RF performance potential of array-based carbon-nanotube transistors—part II: extrinsic results N Paydavosi, JP Rebstock, KD Holland, S Ahmed, AU Alam, ... IEEE transactions on electron devices 58 (7), 1941-1951, 2011	18	2011
BSIM-CMG 108.0. 0: Multi-gate MOSFET compact model: technical manual S Khandelwal, JP Duarte, S Venugopalan, N Paydavosi, DD Lu, CH Lin, ... BSIM Group UC Berkeley, 2014	17*	2014
Bsim-cmg 107.0. 0: Multi-gate mosfet compact model (technical manual) V Sriramkumar, N Paydavosi, J Duarte, D Lu, CH Lin, M Dunga, S Yao, ... University of California, Berkeley, 2013	17	2013
RF performance potential of array-based carbon-nanotube transistors—Part I: Intrinsic results N Paydavosi, AU Alam, S Ahmed, KD Holland, JP Rebstock, ... IEEE transactions on electron devices 58 (7), 1928-1940, 2011	17	2011
Understanding the frequency-and time-dependent behavior of ballistic carbon-nanotube transistors N Paydavosi, KD Holland, MM Zargham, M Vaidyanathan IEEE transactions on nanotechnology 8 (2), 234-244, 2008	17	2008
RF performance limits and operating physics arising from the lack of a bandgap in graphene transistors KD Holland, N Paydavosi, N Neophytou, D Kienle, M Vaidyanathan IEEE transactions on nanotechnology 12 (4), 566-577, 2013	16	2013
BSIM6. 0 MOSFET compact model YS Chauhan, MA Karim, S Venugopalan, H Agarwal, P Thakur, ... Technical Manual, May, 2013	10	2013

El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.

Artículos 1–20

Citas por año

Citas duplicadas

Citas combinadas

Añadir coautoresCoautores

Seguir

Citado por

Coautores