| 17.6 A 21.7-to-26.5 GHz charge-sharing locking quadrature PLL with implicit digital frequency-tracking loop achieving 75fs jitter and− 250dB FoM Y Hu, X Chen, T Siriburanon, J Du, Z Gao, V Govindaraj, A Zhu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2020 | 43 | 2020 |
| A 2.6-to-4.1 GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving-249.4 dB FoM and-59dBc Fractional Spurs Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 380-382, 2022 | 13 | 2022 |
| A low-spur fractional-N PLL based on a time-mode arithmetic unit Z Gao, J He, M Fritz, J Gong, Y Shen, Z Zong, P Chen, G Spalink, B Eitel, ... IEEE Journal of Solid-State Circuits, 2022 | 6 | 2022 |
| A DPLL-Based Phase Modulator Achieving-46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation Z Gao, M Fritz, J He, G Spalink, RB Staszewski, MS Alavi, M Babaie 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 3 | 2022 |
| Design of broadband Class E power amplifier in continuous operation modes Z Gao, C Liu, G Guo, H Chen, C Luo, J Han, L Zhang, Y Yan Electronics letters 49 (25), 1643-1645, 2013 | 3 | 2013 |
| 28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications Z Gao, Y Hu, T Siriburanon, RB Staszewski 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2019 | 1 | 2019 |
| Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop Z Gao, RB Staszewski, M Babaie IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
| A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion Z Gao, M Fritz, G Spalink, RB Staszewski, M Babaie IEEE Journal of Solid-State Circuits, 2023 | | 2023 |
| Amplifier circuit and method of generating an amplified signal RB Staszewski, SM Alavi, M Babaie, Z Gao, J He | | 2023 |
| Pll circuit and method for generating a modulated carrier signal RB Staszewski, SM Alavi, M Babaie, Z Gao, J He | | 2023 |
| Digitally Intensive Frequency Synthesis and Modulation Exploiting a Time-mode Arithmetic Unit Z Gao | | 2023 |
| Circuit arrangement, time-mode arithmetic unit, all-digital phase-locked loop, and corresponding methods RB Staszewski, M Babaie, SM Alavi, Z Gao | | 2023 |
