Madhura Purnaprajna

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Paolo IenneProfessor, EPFLDirección de correo verificada de epfl.ch
Gabriel FalcaoProfessor of Electrical and Computer Engineering, FCTUC, University of Coimbra, IT, PortugalDirección de correo verificada de deec.uc.pt
Mario PorrmannOsnabrück UniversityDirección de correo verificada de porrmann.com
Srinivasan SubramaniyanPhD Student, The Ohio State UniversityDirección de correo verificada de osu.edu
NOVO DavidLIRMM,University of Montpellier, and CNRSDirección de correo verificada de lirmm.fr
Zain ul-AbdinHalmstad UniversityDirección de correo verificada de hh.se
Nesma M. RezkPh.D.Dirección de correo verificada de eng.asu.edu.eg
Joseph R. CavallaroProfessor of Electrical and Computer Engineering, Rice UniversityDirección de correo verificada de rice.edu
Oscar FerrazPhD student, University of Coimbra, ITDirección de correo verificada de co.it.pt
Andreas BurgEPFL - Telecommunications Circuits LaboratoryDirección de correo verificada de epfl.ch
Vitor SilvaProfessor de Engenharia Electrotécnica e de Computadores, Universidade de CoimbraDirección de correo verificada de co.it.pt
Muhsen OwaidaMagic LeapDirección de correo verificada de magicleap.com
Christos D. AntonopoulosProfessor, Department of Electrical & Computer Engineering, University of Thessaly, GreeceDirección de correo verificada de e-ce.uth.gr
Nikolaos BellasProfessor, Department of Electrical and Computer Engineering, University of ThessalyDirección de correo verificada de inf.uth.gr
Tomas NordströmProfessor, Umeå UniversityDirección de correo verificada de umu.se
Marek ReformatUniversity of AlbertaDirección de correo verificada de ualberta.ca
Witold PedryczDirección de correo verificada de ualberta.ca
Hadi Parandeh-AfsharQualcomm Technologies, Inc.Dirección de correo verificada de qti.qualcomm.com
Grace ZgheibProcessor Architecture Lab, EPFLDirección de correo verificada de epfl.ch
Guohui Wang (王国晖)Augmented Reality Research at SnapchatDirección de correo verificada de snapchat.com

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Madhura Purnaprajna

Principal Member Technical Staff, AMD and Professor (on Sabbatical), P.E.S. University

Dirección de correo verificada de pes.edu

Reconfigurable Computing FPGA Architectures Evolutionary Optimisation


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
Recurrent neural networks: An embedded computing perspective NM Rezk, M Purnaprajna, T Nordström, Z Ul-Abdin IEEE Access 8, 57967-57996, 2020	93	2020
Genetic algorithms for hardware–software partitioning and optimal resource allocation M Purnaprajna, M Reformat, W Pedrycz Journal of Systems Architecture 53 (7), 339-354, 2007	73	2007
A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ... IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021	33	2021
Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case G Falcao, M Owaida, D Novo, M Purnaprajna, N Bellas, CD Antonopoulos, ... 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012	29	2012
ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator] E Fung, K Leung, N Parimi, M Purnaprajna, VC Gaudet IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 304-309, 2004	23	2004
Making wide-issue VLIW processors viable on FPGAs M Purnaprajna, P Ienne ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-16, 2012	21	2012
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions M Belwal, M Purnaprajna, TSB Sudarshan 2015 25th International Conference on Field Programmable Logic and …, 2015	20	2015
Power aware reconfigurable multiprocessor for elliptic curve cryptography M Purnaprajna, C Puttmann, M Porrmann Proceedings of the conference on Design, automation and test in Europe, 1462 …, 2008	18	2008
Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs M Owaida, G Falcao, J Andrade, C Antonopoulos, N Bellas, ... ACM Transactions on Embedded Computing Systems (TECS) 14 (2), 1-23, 2015	17	2015
Self-optimization of mpsocs targeting resource efficiency and fault tolerance M Porrmann, M Purnaprajna, C Puttmann 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 467-473, 2009	17	2009
Shadow and-inverter cones H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne 2013 23rd International Conference on Field programmable Logic and …, 2013	16	2013
Compiler-driven reconfiguration of multiprocessors M Hußmann, M Thies, U Kastens, M Purnaprajna, M Porrmann, U Rückert Proceedings of the Workshop on Application Specific Processors (WASP), 3-10, 2007	11	2007
A case for heterogeneous technology-mapping: Soft versus hard multiplexers M Purnaprajna, P Ienne 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013	10	2013
Run-time reconfigurable multiprocessors M Purnaprajna University of Paderborn, 2010	7	2010
CoIn: Accelerated CNN co-inference through data partitioning on heterogeneous devices K Vanishree, A George, S Gunisetty, S Subramanian, S Kashyap, ... 2020 6th International Conference on Advanced Computing and Communication …, 2020	6	2020
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis R Ramakrishnan, AKV Dev, AS Darshik, R Chinchwadkar, M Purnaprajna 2021 34th International Conference on VLSI Design and 2021 20th …, 2021	5	2021
k-core: Hardware Accelerator for k-mer Generation and Counting used in Computational Genomics SM Bose, VS Lalapura, S Saravanan, M Purnaprajna 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019	5	2019
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis M Purnaprajna, M Porrmann, U Rueckert, M Hussmann, M Thies, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3 (3), 1-25, 2010	5	2010
Work in progress: Performance modeling for data distribution in heterogeneous computing systems K Vanishree, M Purnaprajna 2018 International Conference on Compilers, Architectures and Synthesis for …, 2018	4	2018
TileNet: Scalable architecture for high-throughput ternary convolution neural networks using FPGAs SS Vikram, V Pant, M Mody, M Purnaprajna 2018 31st International Conference on VLSI Design and 2018 17th …, 2018	4	2018

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