| SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks KZ Azar, HM Kamali, H Homayoun, A Sasan IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), 97-122, 2019 | 155 | 2019 |
| Full-lock: Hard distributions of sat instances for obfuscating circuits using fully configurable logic and routing blocks HM Kamali, KZ Azar, H Homayoun, A Sasan Proceedings of the 56th Annual Design Automation Conference (DAC) 2019, 1-6, 2019 | 137 | 2019 |
| LUT-lock: A novel LUT-based logic obfuscation for FPGA-bitstream and ASIC-hardware protection HM Kamali, KZ Azar, K Gaj, H Homayoun, A Sasan 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 405-410, 2018 | 119 | 2018 |
| SRCLock: SAT-resistant cyclic logic locking for protecting the hardware S Roshanisefat, H Mardani Kamali, A Sasan Proceedings of the 2018 on Great Lakes Symposium on VLSI (GLSVLSI), 153-158, 2018 | 108 | 2018 |
| Advances in Logic Locking: Past, Present, and Prospects HM Kamali, KZ Azar, F Farahmandi, M Tehranipoor Cryptology ePrint Archive, 2022 | 76 | 2022 |
| Threats on logic locking: A decade later K Zamiri Azar, H Mardani Kamali, H Homayoun, A Sasan Proceedings of the 2019 on Great Lakes Symposium on VLSI (GLSVLSI), 471-476, 2019 | 75 | 2019 |
| InterLock: An Intercorrelated Logic and Routing Locking HM Kamali, KZ Azar, H Homayoun, A Sasan 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-9, 2020 | 67 | 2020 |
| NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures KZ Azar, HM Kamali, H Homayoun, A Sasan 2020 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-9, 2020 | 55 | 2020 |
| Security and complexity analysis of LUT-based obfuscation: From blueprint to reality G Kolhe, HM Kamali, M Naicker, TD Sheaves, H Mahmoodi, PDS Manoj, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 55 | 2019 |
| AdapNoC: A fast and flexible FPGA-based NoC simulator HM Kamali, S Hessabi 2016 Conference on Field Programmable Logic and Applications (FPL), 1-8, 2016 | 37 | 2016 |
| DFSSD: Deep faults and shallow state duality, a provably strong obfuscation solution for circuits with restricted access to scan chain S Roshanisefat, HM Kamali, KZ Azar, SMP Dinakarrao, N Karimi, ... 2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020 | 35 | 2020 |
| COMA: Communication and Obfuscation Management Architecture KZ Azar, F Farahmand, HM Kamali, S Roshanisefat, H Homayoun, ... Symposium on Research in Attacks, Intrusions and Defenses (RAID) 2019, 181-195, 2019 | 35 | 2019 |
| DuCNoC: A high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architecture HM Kamali, KZ Azar, S Hessabi IEEE Transactions on Computers 67 (2), 208-221, 2017 | 35 | 2017 |
| RANE: An open-source formal de-obfuscation attack for reverse engineering of logic encrypted circuits S Roshanisefat, H Mardani Kamali, H Homayoun, A Sasan Proceedings of the 2021 on Great Lakes Symposium on VLSI, 221-228, 2021 | 33 | 2021 |
| SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain S Roshanisefat, HM Kamali, H Homayoun, A Sasan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 954-967, 2020 | 30 | 2020 |
| From cryptography to logic locking: A survey on the architecture evolution of secure scan chains KZ Azar, HM Kamali, H Homayoun, A Sasan IEEE Access 9, 73133-73151, 2021 | 29 | 2021 |
| SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption HM Kamali, KZ Azar, H Homayoun, A Sasan 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-8, 2020 | 29 | 2020 |
| Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits KZ Azar, HM Kamali, S Roshanisefat, H Homayoun, CP Sotiriou, A Sasan IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-14, 2021 | 26 | 2021 |
| On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic HM Kamali, KZ Azar, H Homayoun, A Sasan Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI), 1-6, 2020 | 26 | 2020 |
| SMART: A scalable mapping and routing technique for power-gating in NoC routers H Farrokhbakht, HM Kamali, S Hessabi Proceedings of IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 15, 2017 | 19 | 2017 |
Kimia Zamiri AzarResearch Assistant Professor at University of FloridaDirección de correo verificada de ufl.edu
