| Power-based side-channel instruction-level disassembler J Park, X Xu, Y Jin, D Forte, M Tehranipoor Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 81 | 2018 |
| RTL-PSC: Automated power side-channel leakage assessment at register-transfer level M He, J Park, A Nahiyan, A Vassilev, Y Jin, M Tehranipoor 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 60 | 2019 |
| Using Power Clues to Hack IoT Devices: The power side channel provides for instruction-level disassembly J Park, A Tyagi IEEE Consumer Electronics Magazine 6 (3), 92-102, 2017 | 47 | 2017 |
| Script: A cad framework for power side-channel vulnerability assessment using information flow tracking and pattern generation A Nahiyan, J Park, M He, Y Iskander, F Farahmandi, D Forte, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020 | 35 | 2020 |
| Leveraging side-channel information for disassembly and security J Park, F Rahman, A Vassilev, D Forte, M Tehranipoor ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (1), 1-21, 2019 | 32 | 2019 |
| PSC-TG: RTL power side-channel leakage assessment with test pattern generation T Zhang, J Park, M Tehranipoor, F Farahmandi 2021 58th ACM/IEEE Design Automation Conference (DAC), 709-714, 2021 | 30 | 2021 |
| Power side-channel leakage assessment framework at register-transfer level N Pundir, J Park, F Farahmandi, M Tehranipoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (9 …, 2022 | 27 | 2022 |
| PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms. J Park, NN Anandakumar, D Saha, D Mehta, N Pundir, F Rahman, ... IACR Cryptol. ePrint Arch. 2022, 527, 2022 | 23 | 2022 |
| Real-time instruction-level verification of remote IoT/CPS devices via side channels Y Bai, J Park, M Tehranipoor, D Forte Discover Internet of Things 2 (1), 1, 2022 | 18 | 2022 |
| QEC: A quantum entropy chip and its applications J Park, S Cho, T Lim, M Tehranipoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 17 | 2020 |
| t-Private logic synthesis on FPGAs J Park, A Tyagi 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 63-68, 2012 | 15 | 2012 |
| Towards making private circuits practical: DPA resistant private circuits J Park, A Tyagi 2014 IEEE Computer Society Annual Symposium on VLSI, 528-533, 2014 | 13 | 2014 |
| Secure physical design S Dey, J Park, N Pundir, D Saha, AM Shuvo, D Mehta, N Asadi, F Rahman, ... Cryptology ePrint Archive, 2022 | 12 | 2022 |
| Rascv2: Enabling remote access to side-channels for mission critical and iot systems Y Bai, A Stern, J Park, M Tehranipoor, D Forte ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (6 …, 2022 | 11 | 2022 |
| Ldtfi: Layout-aware timing fault-injection attack assessment against differential fault analysis AM Shuvo, N Pundir, J Park, F Farahmandi, M Tehranipoor 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 134-139, 2022 | 9 | 2022 |
| Security metrics for power based SCA resistant hardware implementation J Park, A Tyagi 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 9 | 2016 |
| CAD framework for power side-channel vulnerability assessment MM Tehranipoor, A Nahiyan, DJ Forte, J Park US Patent 11,475,168, 2022 | 8 | 2022 |
| Psc-tg: Rtl power side-channel leakage assessment with test pattern generation. In 2021 58th ACM/IEEE Design Automation Conference (DAC) T Zhang, J Park, M Tehranipoor, F Farahmandi IEEE, 2021 | 5 | 2021 |
| RASC: Enabling Remote Access to Side-Channels for Mission Critical Systems A Stern, K Yang, J Vosatka, A Duncan, J Park, D Forte, M Tehranipoor GOMACTech-19 51 (Artificial Intelligence & Cyber Security), 2019 | 5 | 2019 |
| ATAVE: A framework for automatic timing attack vulnerability evaluation J Park, M Corba, AE de la Sema, RL Vigeant, M Tehranipoor, S Bhunia 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 5 | 2017 |
