A new low-power architecture design for distributed arithmetic unit in FIR filter implementation SF Ghamkhari, MB Ghaznavi-Ghoushchi Circuits, Systems, and Signal Processing 33, 1245-1259, 2014 | 11 | 2014 |
A low-power low-area architecture design for distributed arithmetic (DA) unit SF Ghamkhari, MB Ghaznavi-Ghoushchi 20th Iranian Conference on Electrical Engineering (ICEE2012), 232-237, 2012 | 9 | 2012 |
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits FS Ayatollahi, MB Ghaznavi-Ghoushchi, Naser Mohammadzadeh, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2022 | 4 | 2022 |
A New Low-Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity SF Ghamkhari, MB Ghaznavi-Ghoushchi Circuits, Systems, and Signal Processing (CSSP), 1-17, 2020 | 2 | 2020 |
A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller SF Ghamkhari, MB Ghaznavi‐Ghoushchi International Journal of Circuit Theory and Applications (IJCTA), 2021 | 1 | 2021 |
A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs SF Ghamkhari, MB Ghaznavi-Ghoushchi صنايع الکترونيک 11 (3), 2020 | | 2020 |
Design and Implementation of Reconfigurable Integrated FPGA-based PSK Demodulator SF Ghamkhari, S Karimian International Symposium on Telecommunications (IST), ICT Research Institute, 1-5, 2020 | | 2020 |
A New Low-Power Schema for DA-based FIR filters front-end shift-register arrays utilizing statistical properties of massive inputs SF Ghamkhari, MB Ghaznavi-Ghoushchi Electronics Industries (E.I.), 1-14, 2020 | | 2020 |