Understanding delta-sigma data converters S Pavan, R Schreier, GC Temes
John Wiley & Sons, 2017
578 2017 Widely programmable high-frequency continuous-time filters in digital CMOS technology S Pavan, YP Tsividis, K Nagaraj
IEEE Journal of Solid-State Circuits 35 (4), 503-511, 2000
181 2000 A Power Optimized Continuous-Time S Pavan, N Krishnapura, R Pandarinathan, P Sankar
IEEE Journal of Solid-State Circuits 43 (2), 351-360, 2008
151 2008 Low power design techniques for single-bit audio continuous-time delta sigma ADCs using FIR feedback A Sukumaran, S Pavan
IEEE Journal of Solid-State Circuits 49 (11), 2515-2525, 2014
141 2014 Design Techniques for Wideband Single-Bit Continuous-Time P Shettigar, S Pavan
IEEE Journal of Solid-State Circuits 47 (12), 2865-2879, 2012
141 2012 Fundamental limitations of continuous-time delta–sigma modulators due to clock jitter K Reddy, S Pavan
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (10), 2184-2194, 2007
116 2007 A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS process K Nagaraj, DA Martin, M Wolfe, R Chattopadhyay, S Pavan, J Cancio, ...
IEEE Journal of Solid-State Circuits 35 (12), 1760-1768, 2000
115 2000 Next-generation delta-sigma converters: Trends and perspectives JM de la Rosa, R Schreier, KP Pun, S Pavan
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (4 …, 2015
105 2015 High frequency continuous time filters in digital CMOS processes S Pavan, Y Tsividis
Springer Science & Business Media, 2007
103 2007 Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique S Pavan, P Sankar
IEEE Journal of Solid-State Circuits 45 (7), 1365-1379, 2010
99 2010 A 15mW 3.6 GS/s CT-δσ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS P Shettigar, S Pavan
2012 IEEE International Solid-State Circuits Conference, 156-158, 2012
92 2012 Excess loop delay compensation in continuous-time delta-sigma modulators S Pavan
IEEE Transactions on Circuits and Systems II: express briefs 55 (11), 1119-1123, 2008
89 2008 Analysis and design of continuous-time delta–sigma converters incorporating chopping S Billa, A Sukumaran, S Pavan
IEEE Journal of Solid-State Circuits 52 (9), 2350-2361, 2017
87 2017 Widely Programmable High-Frequency Active RC Filters in CMOS Technology T Laxminidhi, V Prasadu, S Pavan
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (2), 327-336, 2008
78 2008 Active-RC filters using the Gm-assisted OTA-RC technique SV Thyagarajan, S Pavan, P Sankar
IEEE Journal of Solid-State Circuits 46 (7), 1522-1533, 2011
77 2011 Systematic design centering of continuous time oversampling converters S Pavan
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (3), 158-162, 2010
74 2010 Transmission Line based FIR Structures for High Speed Adaptive Equalization R Tiruvuru, S Pavan
2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp.-1054, 2006
66 2006 A 9-GS/s 1.125-GHz BW oversampling continuous-time pipeline ADC achieving− 164-dBFS/Hz NSD H Shibata, V Kozlov, Z Ji, A Ganesan, H Zhu, D Paterson, J Zhao, S Patil, ...
IEEE Journal of Solid-State Circuits 52 (12), 3219-3234, 2017
60 2017 A 16 MHz BW 75 dB DR CT V Singh, N Krishnapura, S Pavan, B Vigraham, D Behera, N Nigania
IEEE Journal of Solid-State Circuits 47 (8), 1884-1895, 2012
60 2012 Alias Rejection of Continuous-Time S Pavan
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (2), 233-243, 2010
57 2010 