| Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Liu, Y Wang, Y Xie ACM SIGARCH Computer Architecture News 44 (3), 27-39, 2016 | 797 | 2016 |
| Overcoming the challenges of crossbar resistive memory architectures C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 255 | 2015 |
| Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems M Poremba, T Zhang, Y Xie IEEE Computer Architecture Letters 14 (2), 140-143, 2015 | 156 | 2015 |
| Half-DRAM: A High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation T Zhang, K Chen, C Xu, G Sun, T Wang, Y Xie 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 115 | 2014 |
| Leap: a low energy assisted gps for trajectory-based services HS Ramos, T Zhang, J Liu, NB Priyantha, A Kansal Proceedings of the 13th international conference on Ubiquitous computing …, 2011 | 55 | 2011 |
| Morphcache: A reconfigurable adaptive multi-level cache hierarchy S Srikantaiah, E Kultursay, T Zhang, M Kandemir, MJ Irwin, Y Xie 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 48 | 2011 |
| CREAM: A concurrent-refresh-aware DRAM memory architecture T Zhang, M Poremba, C Xu, G Sun, Y Xie 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 43 | 2014 |
| A 3D SoC design for H. 264 application with on-chip DRAM stacking T Zhang, K Wang, Y Feng, Y Chen, Q Li, B Shao, J Xie, X Song, L Duan, ... 2010 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2010 | 36 | 2010 |
| Arithmetic unit design using 180nm TSV-based 3D stacking technology J Ouyang, G Sun, Y Chen, L Duan, T Zhang, Y Xie, MJ Irwin 2009 IEEE International Conference on 3D System Integration, 1-4, 2009 | 35 | 2009 |
| A customized design of DRAM controller for on-chip 3D DRAM stacking T Zhang, K Wang, Y Feng, X Song, L Duan, Y Xie, X Cheng, YL Lin IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 32 | 2010 |
| Sparse tensor core: Algorithm and hardware co-design for vector-wise sparse neural networks on modern gpus M Zhu, T Zhang, Z Gu, Y Xie Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 27 | 2019 |
| Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing P Chi, C Xu, T Zhang, X Dong, Y Xie 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 301-308, 2014 | 27 | 2014 |
| 3D-SWIFT: A high-performance 3D-stacked wide IO DRAM T Zhang, C Xu, K Chen, G Sun, Y Xie Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, 51-56, 2014 | 22 | 2014 |
| Thermomechanical stress-aware management for 3D IC designs Q Zou, T Zhang, E Kursun, Y Xie 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 19* | 2013 |
| An efficient run-time encryption scheme for non-volatile main memory X Zhang, C Zhang, G Sun, J Di, T Zhang 2013 International conference on compilers, architecture and synthesis for …, 2013 | 15 | 2013 |
| Rc-nvm: Enabling symmetric row and column memory accesses for in-memory databases P Wang, S Li, G Sun, X Wang, Y Chen, H Li, J Cong, N Xiao, T Zhang 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 10 | 2018 |
| Eflops: Algorithm and system co-design for a high performance distributed training platform J Dong, Z Cao, T Zhang, J Ye, S Wang, F Feng, L Zhao, X Liu, L Song, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 8 | 2020 |
| Building a low latency, highly associative dram cache with the buffered way predictor Z Wang, DA Jiménez, T Zhang, GH Loh, Y Xie 2016 28th International Symposium on Computer Architecture and High …, 2016 | 7 | 2016 |
| Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision M Poremba, T Zhang, Y Xie Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 7 | 2016 |
| Processing-in-memory in ReRAM-based main memory P Chi, S Li, C Xu, T Zhang, J Zhao, Y Wang, Y Liu, Y Xie SEAL-lab Technical Report, 2015 | 7 | 2015 |
Yuan XieProfessor of University of California at Santa BarbaraDirección de correo verificada de ece.ucsb.edu
