| Soft error rate improvements in 14-nm technology featuring second-generation 3D tri-gate transistors N Seifert, S Jahinuzzaman, J Velamala, R Ascazubi, N Patel, B Gill, ... IEEE Transactions on Nuclear Science 62 (6), 2570-2577, 2015 | 128 | 2015 |
| Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging E Mintarno, J Skaf, R Zheng, JB Velamala, Y Cao, S Boyd, RW Dutton, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 114 | 2011 |
| Compact modeling of statistical BTI under trapping/detrapping JB Velamala, KB Sutaria, H Shimizu, H Awano, T Sato, G Wirth, Y Cao IEEE transactions on electron devices 60 (11), 3645-3654, 2013 | 91 | 2013 |
| Cross-layer modeling and simulation of circuit reliability Y Cao, J Velamala, K Sutaria, MSW Chen, J Ahlbin, IS Esqueda, M Bajura, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 81 | 2013 |
| Physics matters: statistical aging prediction under trapping/detrapping JB Velamala, K Sutaria, T Sato, Y Cao Proceedings of the 49th Annual Design Automation Conference, 139-144, 2012 | 66 | 2012 |
| Circuit aging prediction for low-power operation R Zheng, J Velamala, V Reddy, V Balakrishnan, E Mintarno, S Mitra, ... 2009 IEEE Custom Integrated Circuits Conference, 427-430, 2009 | 61 | 2009 |
| Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction JB Velamala, KB Sutaria, T Sato, Y Cao 2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 2.1-2F. 2.5, 2012 | 55 | 2012 |
| Optimized self-tuning for circuit aging E Mintarno, J Skaf, R Zheng, J Velamala, Y Cao, S Boyd, RW Dutton, ... 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 50 | 2010 |
| Failure diagnosis of asymmetric aging under NBTI JB Velamala, V Ravi, Y Cao 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 428-433, 2011 | 34 | 2011 |
| Aging statistics based on trapping/detrapping: Compact modeling and silicon validation KB Sutaria, JB Velamala, CH Kim, T Sato, Y Cao IEEE Transactions on Device and Materials Reliability 14 (2), 607-615, 2014 | 33 | 2014 |
| Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets N Seifert, S Jahinuzzaman, J Velamala, N Patel 2015 IEEE International Reliability Physics Symposium, 2C. 1.1-2C. 1.6, 2015 | 31 | 2015 |
| Design sensitivity of single event transients in scaled logic circuits J Velamala, R LiVolsi, M Torres, Y Cao Proceedings of the 48th Design Automation Conference, 694-699, 2011 | 27 | 2011 |
| IRT: A modeling system for single event upset analysis that captures charge sharing effects K Foley, N Seifert, JB Velamala, WG Bennett, S Gupta International Reliability Physics Symposium, 1.1-1.9, 2014 | 26 | 2014 |
| Failure analysis of asymmetric aging under NBTI JB Velamala, KB Sutaria, VS Ravi, Y Cao IEEE Transactions on Device and Materials Reliability 13 (2), 340-349, 2012 | 25 | 2012 |
| Circuit-level delay modeling considering both TDDB and NBTI H Luo, X Chen, J Velamala, Y Wang, Y Cao, V Chandra, Y Ma, H Yang 2011 12th International Symposium on Quality Electronic Design, 1-8, 2011 | 23 | 2011 |
| Statistical aging under dynamic voltage scaling: A logarithmic model approach JB Velamala, K Sutaria, H Shimizu, H Awano, T Sato, Y Cao Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 21 | 2012 |
| Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction JB Velamala, KB Sutaria, H Shimuzu, H Awano, T Sato, G Wirth, Y Cao 2013 IEEE international reliability physics symposium (IRPS), CM. 3.1-CM. 3.5, 2013 | 17 | 2013 |
| Compact modeling of BTI for circuit reliability analysis KB Sutaria, JB Velamala, A Ramkumar, Y Cao Circuit design for reliability, 93-119, 2015 | 15 | 2015 |
| A self-tuning design methodology for power-efficient multi-core systems J Sun, R Zheng, J Velamala, Y Cao, R Lysecky, K Shankar, J Roveda ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (1 …, 2013 | 14 | 2013 |
| The impact of correlation between NBTI and TDDB on the performance of digital circuits H Luo, Y Wang, J Velamala, Y Cao, Y Xie, H Yang 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 9 | 2011 |
