Socrates Vamvakos
Socrates Vamvakos
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Digital phase locked loop with dithering
K Waheed, M Sheba, RB Staszewski, S Vamvakos
US Patent 7,786,913, 2010
612010
Digital phase locked loop with dithering
K Waheed, M Sheba, RB Staszewski, S Vamvakos
US Patent 7,920,081, 2011
492011
On the departure process of a leaky bucket system with long-range dependent input traffic
S Vamvakos, V Anantharam
Queueing Systems 28 (1-3), 191-214, 1998
481998
Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences
K Waheed, RB Staszewski, F Dulger, MS Ullah, SD Vamvakos
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2051-2060, 2011
352011
Noise analysis of time-to-digital converter in all-digital PLLs
SD Vamvakos, RB Staszewski, M Sheba, K Waheed
2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and …, 2006
292006
Digital phase locked loop with dithering
K Waheed, M Sheba, RB Staszewski, S Vamvakos
US Patent App. 13/038,885, 2011
212011
PLL on-chip jitter measurement: Analysis and design
S Vamvakos, V Stojanovic, J Zerbe, C Werner, D Draper, B Nikolic
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 73-74, 2006
152006
Discrete-time, linear periodically time-variant phase-locked loop model for jitter analysis
SD Vamvakos, V Stojanovic, B Nikolic
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (6), 1211-1224, 2011
142011
Phase-locked loop architecture for adaptive jitter optimization
SD Vamvakos, C Werner, B Nikolic
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
132004
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications
SD Vamvakos, CR Gauthier, C Rao, KR Canagasaby, P Choudhary, ...
2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012
122012
A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop
SD Vamvakos, C Boecker, E Groen, A Wang, S Desai, S Irwin, V Rao, ...
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014
72014
Modelling, parameter assessment and multiplexing analysis of bursty sources with hyper-exponentially distributed bursts
N Mitrou, S Vamvakos, K Kontovasilis
Computer networks and ISDN systems 27 (7), 1175-1192, 1995
71995
Discrete-time, cyclostationary phase-locked loop model for jitter analysis
SD Vamvakos, V Stojanovic, B Nikolic
2009 IEEE Custom Integrated Circuits Conference, 637-640, 2009
62009
A 576 Mb DRAM with 16-channel 10.3125 Gbps serial I/O and 14.5 ns latency
SD Vamvakos, B Kleveland, D Sikdar, BK Ahuja, H Lin, J Balachandran, ...
2012 Proceedings of the ESSCIRC (ESSCIRC), 458-461, 2012
42012
An intelligent RAM with serial I/Os
B Kleveland, MJ Miller, RB David, J Patel, R Chopra, DK Sikdar, J Kumala, ...
IEEE Micro 33 (6), 56-65, 2013
32013
Analysis, measurement and optimization of jitter in phase-locked loops
SD Vamvakos
University of California, Berkeley, 2005
22005
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
E Groen, C Boecker, M Hossain, R Vu, S Vamvakos, H Lin, S Li, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 120-122, 2020
12020
A 2.488–11.2 áGb/s SerDes in 40ánm low-leakage CMOS with multi-protocol compatibility for FPGA applications
SD Vamvakos, CR Gauthier, C Rao, A Wang, KR Canagasaby, ...
Analog Integrated Circuits and Signal Processing 78 (2), 259-273, 2014
12014
A 4× 112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET
H Lin, C Boecker, M Hossain, S Tangirala, R Vu, S Vamvakos, E Groen, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
2020
Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator
SD Vamvakos, J Zhuang, K Waheed
2009 IEEE Dallas Circuits and Systems Workshop (DCAS), 1-4, 2009
2009
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Artículos 1–20