| A fast bootstrapped switch for high-speed high-resolution A/D converter G Huang, P Lin 2010 IEEE Asia Pacific Conference on Circuits and Systems, 382-385, 2010 | 25 | 2010 |
| A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS B Peng, G Huang, H Li, P Wan, P Lin 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 24 | 2011 |
| Analog assisted multichannel digital postcorrection for time-interleaved ADCs G Huang, C Yu, A Zhu IEEE Transactions on Circuits and Systems II: Express Briefs 63 (8), 773-777, 2016 | 11 | 2016 |
| A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique G Huang, P Lin Microelectronics Journal 43 (12), 941-948, 2012 | 10 | 2012 |
| A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS G Huang, P Lin Analog Integrated Circuits and Signal Processing 77, 285-289, 2013 | 8 | 2013 |
| A DC-offset cancellation circuit for PGA in baseband communication G Huang, Y Wu, C Zhong, P Lin 2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011 | 5 | 2011 |
| Simplified Volterra series based background calibration for high speed high resolution pipelined ADCs G Huang, B Peng, A Zhu 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 4 | 2015 |
| An 8.38 fJ/conversion-step 0.6 V 8-b 4.35 MS/s asynchronous SAR ADC in 65 nm CMOS G Huang, P Lin Analog Integrated Circuits and Signal Processing 73, 265-272, 2012 | 4 | 2012 |
| 1.1‐V, 8‐bit, 12 MS/s asynchronous reference‐free successive‐approximation‐register analogue‐to‐digital converter in 0.18 μm CMOS with separated capacitor arrays G Huang, P Lin IET Circuits, Devices & Systems 7 (1), 1-8, 2013 | 2 | 2013 |
| A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS G Huang, P Lin Journal of Circuits, Systems and Computers 22 (04), 1350017, 2013 | 1 | 2013 |
| A 5-bit 125-MS/s 367-µW ADC in 65-nm CMOS G Huang, P Lin 2012 IEEE 55th International Midwest Symposium on Circuits and Systems …, 2012 | 1 | 2012 |
| Design and Implementation of Digital Calibrated Pipelined ADC B Peng, P Wan, H Li, G Huang, P Lin Bandaoti Jishu(Semiconductor Technology) 36 (9), 701-704, 2011 | | 2011 |
| A programmable gain amplifier with DC-offset cancellation for power line communication C Zhong, D Zhu, G Huang, P Wan, P Lin 2010 10th IEEE International Conference on Solid-State and Integrated …, 2010 | | 2010 |
