Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates H Mertens, R Ritzenthaler, A Hikavyy, MS Kim, Z Tao, K Wostyn, SA Chew, ... 2016 IEEE symposium on VLSI technology, 1-2, 2016 | 222 | 2016 |
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ... 2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016 | 166 | 2016 |
First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices R Delhougne, A Arreghini, E Rosseel, A Hikavyy, E Vecchio, L Zhang, ... 2018 IEEE Symposium on VLSI Technology, 203-204, 2018 | 165 | 2018 |
Fabrication and Analysis of a Heterojunction Line Tunnel FET AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ... IEEE Transactions on Electron Devices 61 (3), 707-715, 2014 | 152 | 2014 |
Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs A Vandooren, D Leonelli, R Rooyackers, A Hikavyy, K Devriendt, ... Solid-State Electronics 83, 50-55, 2013 | 150 | 2013 |
Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography MJH Van Dal, N Collaert, G Doornbos, G Vellianitis, G Curatola, ... 2007 IEEE symposium on VLSI technology, 110-111, 2007 | 106 | 2007 |
First monolithic integration of 3d complementary fet (cfet) on 300mm wafers S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ... 2020 Ieee Symposium on Vlsi Technology, 1-2, 2020 | 84 | 2020 |
Advancing CMOS beyond the Si roadmap with Ge and III/V devices M Heyns, A Alian, G Brammertz, M Caymax, YC Chang, LK Chu, ... 2011 International Electron Devices Meeting, 13.1. 1-13.1. 4, 2011 | 84 | 2011 |
Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition L Witters, H Arimura, F Sebaai, A Hikavyy, AP Milenin, R Loo, ... IEEE transactions on electron devices 64 (11), 4587-4593, 2017 | 80 | 2017 |
First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs E Capogreco, L Witters, H Arimura, F Sebaai, C Porret, A Hikavyy, R Loo, ... IEEE Transactions on Electron Devices 65 (11), 5145-5150, 2018 | 72 | 2018 |
Atomic layer deposition of ZnS thin films based on diethyl zinc and hydrogen sulfide G Stuyven, P De Visschere, A Hikavyy, K Neyts Journal of crystal growth 234 (4), 690-698, 2002 | 71 | 2002 |
Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 66 | 2021 |
Characterization of epitaxial Si: C: P and Si: P layers for source/drain formation in advanced bulk FinFETs E Rosseel, HB Profijt, AY Hikavyy, J Tolle, S Kubicek, G Mannaert, ... ECS Transactions 64 (6), 977, 2014 | 62 | 2014 |
A new complementary hetero-junction vertical tunnel-FET integration scheme R Rooyackers, A Vandooren, AS Verhulst, A Walke, K Devriendt, ... 2013 IEEE International Electron Devices Meeting, 4.2. 1-4.2. 4, 2013 | 61 | 2013 |
Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process L Witters, J Mitard, R Loo, G Eneman, H Mertens, DP Brunco, SH Lee, ... 2013 IEEE International Electron Devices Meeting, 20.4. 1-20.4. 4, 2013 | 58 | 2013 |
Selective epitaxial growth of high-P Si: P for source/drain formation in advanced Si nFETs E Rosseel, SK Dhayalan, AY Hikavyy, R Loo, HB Profijt, D Kohen, ... ECS Transactions 75 (8), 347, 2016 | 56 | 2016 |
Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high … H Mertens, R Ritzenthaler, H Arimura, J Franco, F Sebaai, A Hikavyy, ... 2015 Symposium on VLSI Technology (VLSI Technology), T142-T143, 2015 | 51 | 2015 |
15nm-WFINhigh-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process J Mitard, L Witters, R Loo, SH Lee, JW Sun, J Franco, LÅ Ragnarsson, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 51 | 2014 |
Stress simulations for optimal mobility group IV p-and nMOS FinFETs for the 14 nm node and beyond G Eneman, DP Brunco, L Witters, B Vincent, P Favia, A Hikavyy, ... 2012 International Electron Devices Meeting, 6.5. 1-6.5. 4, 2012 | 50 | 2012 |
Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect L Witters, J Mitard, R Loo, S Demuynck, SA Chew, T Schram, Z Tao, ... 2015 Symposium on VLSI Technology (VLSI Technology), T56-T57, 2015 | 49 | 2015 |