| An ATPG method for double stuck-at faults by analyzing propagation paths of single faults P Wang, CJ Moore, AM Gharehbaghi, M Fujita IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 1063-1074, 2017 | 15 | 2017 |
| An automatic test pattern generation method for multiple stuck-at faults by incrementally extending the test patterns P Wang, AM Gharehbaghi, M Fujita IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 6 | 2019 |
| An incremental automatic test pattern generation method for multiple stuck-at faults P Wang, AM Gharehbaghi, M Fujita 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 6 | 2019 |
| Automatic test pattern generation for double stuck-at faults based on test patterns of single faults P Wang, AM Gharehbaghi, M Fujita 20th International Symposium on Quality Electronic Design (ISQED), 284-290, 2019 | 6 | 2019 |
| Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults CJ Moore, P Wang, AM Gharehbaghi, M Fujita 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 4 | 2017 |
| A Hardware Architecture of Particle Swarm Optimization. Y Lu, P Wang, J Qin J. Comput. 12 (5), 442-450, 2017 | 2 | 2017 |
| Two-Level Pipeline Structure for Particle Swarm Optimization K Fan, KT Chen, P Wang, T Baba Journal of Signal Processing 19 (4), 115-118, 2015 | 1 | 2015 |
| A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality P Wang, AM Gharehbaghi, M Fujita IPSJ Transactions on System and LSI Design Methodology 13, 35-38, 2020 | | 2020 |
| (VLSI 設計技術)--(デザインガイア 2019: VLSI 設計の新しい大地) P Wang, AM Gharehbaghi, M Fujita 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 119 (282), 19-22, 2019 | | 2019 |
| A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults P Wang, AM Gharehbaghi, M Fujita IEICE Technical Report; IEICE Tech. Rep. 119 (282), 19-22, 2019 | | 2019 |
