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Junyi Liu
Junyi Liu
Microsoft Research
Dirección de correo verificada de microsoft.com - Página principal
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Redundancy-reduced mobilenet acceleration on reconfigurable logic for imagenet classification
J Su, J Faraone, J Liu, Y Zhao, DB Thomas, PHW Leong, PYK Cheung
Applied Reconfigurable Computing. Architectures, Tools, and Applications …, 2018
772018
Loop splitting for efficient pipelining in high-level synthesis
J Liu, J Wickerson, GA Constantinides
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016
532016
Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs
Y Zhao, X Gao, X Guo, J Liu, E Wang, R Mullins, PYK Cheung, ...
2019 International Conference on Field-Programmable Technology (ICFPT), 45-53, 2019
442019
Offline synthesis of online dependence testing: Parametric loop pipelining for HLS
J Liu, S Bayliss, GA Constantinides
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015
432015
Polyhedral-based Dynamic Loop Pipelining for High-Level Synthesis
J Liu, J Wickerson, S Bayliss, GA Constantinides
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
362017
Parallel implementations of the fast gradient method for high-speed MPC
H Peyrl, A Zanarini, T Besselmann, J Liu, MA Boéchat
Control Engineering Practice 33, 22-34, 2014
322014
FPGA implementation of an interior point method for high-speed model predictive control
J Liu, H Peyrl, A Burg, GA Constantinides
2014 24th International Conference on Field Programmable Logic and …, 2014
202014
An architecture for solving quadratic programs with the fast gradient method on a field programmable gate array
MA Boéchat, J Liu, H Peyrl, A Zanarini, T Besselmann
21st Mediterranean Conference on Control and Automation, 1557-1562, 2013
142013
An FPGA implementation of the fast gradient method for solving the model predictive pulse pattern control problem
H Peyrl, J Liu, T Geyer
2013 IEEE International Symposium on Sensorless Control for Electrical …, 2013
132013
Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis
J Liu, J Wickerson, GA Constantinides
Field Programmable Logic and Applications (FPL), 2017 27th International …, 2017
122017
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies
J Liu, J Wickerson, S Bayliss, GA Constantinides
Signals, Systems, and Computers, 2017 51st Asilomar Conference on, 126-130, 2017
42017
Honeycomb: ordered key-value store acceleration on an FPGA-based SmartNIC
J Liu, A Dragojević, S Fleming, A Katsarakis, D Korolija, I Zablotchi, H Ng, ...
IEEE Transactions on Computers, 2023
32023
Parametric polyhedral optimisation for high-level synthesis
J Liu
https://spiral.imperial.ac.uk/handle/10044/1/64814, 2017
2017
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Artículos 1–13