| An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems Y Kim, Y Zhang, P Li 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 130-137, 2013 | 179 | 2013 |
| A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing Y Kim, Y Zhang, P Li ACM Journal on Emerging Technologies in Computing Systems 11 (4), 38:1-38:25, 2015 | 99 | 2015 |
| A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning Y Kim, Y Zhang, P Li 2012 IEEE International SOC Conference, 328-333, 2012 | 92 | 2012 |
| Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing Y Kim, Y Zhang, P Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015 | 53 | 2015 |
| Design and Analysis of an Approximate Adder with Hybrid Error Reduction H Seo, YS Yang, Y Kim Electronics 9 (3), 471, 2020 | 47 | 2020 |
| A Novel Approximate Adder Design using Error Reduced Carry Prediction and Constant Truncation J Lee, H Seo, H Seok, Y Kim IEEE Access, 2021 | 25 | 2021 |
| Neuromorphic processors with memristive synapses: Synaptic interface and architectural exploration Q Wang, Y Kim, P Li ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 1-22, 2016 | 25 | 2016 |
| A 0.38 V near/sub-V T digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process Y Kim, P Li IET Circuits, Devices & Systems 7 (1), 31-41, 2013 | 24 | 2013 |
| Recent Trend of Neuromorphic Computing Hardware: Intel's Neuromorphic System Perspective YS Yang, Y Kim 2020 International SoC Design Conference (ISOCC), 218-219, 2020 | 20 | 2020 |
| An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration Y Kim, P Li Quality Electronic Design (ISQED), 2012 13th International Symposium on, 151-158, 2012 | 18 | 2012 |
| Approximate adder design with simplified lower-part approximation J Lee, H Seo, Y Kim, Y Kim IEICE Electronics Express 17 (15), 20200218-20200218, 2020 | 16 | 2020 |
| An Accuracy Enhanced Error Tolerant Adder with Carry Prediction for Approximate Computing Y Kim IEIE Transactions on Smart Processing & Computing 8 (4), 324-330, 2019 | 16 | 2019 |
| A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification Q Wang, P Li, Y Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8 …, 2015 | 16 | 2015 |
| A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process YH Kwak, Y Kim, S Hwang, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (2), 303-313, 2013 | 16 | 2013 |
| A Novel Approximate Adder with Enhanced Low-cost Carry Prediction for Error Tolerant Computing Y Kim IEIE Transactions on Smart Processing & Computing 8 (6), 506-510, 2019 | 13 | 2019 |
| Piecewise linear modulation technique for spread spectrum clock generation M Song, S Ahn, I Jung, Y Kim, C Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (7 …, 2012 | 13 | 2012 |
| Architectural Design Exploration for Neuromorphic Processors with Memristive Synapses Q Wang, Y Kim, P Li IEEE International Conference on Nanotechnology, 962-966, 2014 | 12 | 2014 |
| COREA: Delay-and Energy-Efficient Approximate Adder Using Effective Carry Speculation H Seok, H Seo, J Lee, Y Kim Electronics 10 (18), 2234, 2021 | 11 | 2021 |
| A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation M Song, S Ahn, I Jung, Y Kim, C Kim 2008 IEEE Custom Integrated Circuits Conference, 455-458, 2008 | 11 | 2008 |
| Design of a Low-Cost Approximate Adder with a Zero Truncation J Lee, H Seo, Y Kim, Y Kim 2020 International SoC Design Conference (ISOCC), 69-70, 2020 | 10 | 2020 |
Hyoju SeoKyungpook National University Computer Science & EngineeringDirección de correo verificada de knu.ac.kr
