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Saurabh Sinha
Saurabh Sinha
Engineer, Apple
Dirección de correo verificada de apple.com
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ASAP7: A 7-nm finFET predictive process design kit
LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ...
Microelectronics Journal 53, 105-115, 2016
4772016
Exploring sub-20nm FinFET design with predictive technology models
S Sinha, G Yeric, V Chandra, B Cline, Y Cao
Proceedings of the 49th Annual Design Automation Conference, 283-288, 2012
3692012
Compact modeling of carbon nanotube transistor for early stage process-design exploration
A Balijepalli, S Sinha, Y Cao
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
1132007
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM
T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan
IEEE Electron Device Letters 38 (8), 1161-1164, 2017
932017
Correlated electron switch programmable fabric
L Shifren, G Yeric, S Sinha, B Cline, V Chandra
US Patent 10,056,143, 2018
922018
Tuning the permeability of permalloy films for on-chip inductor applications
T Dastagir, W Xu, S Sinha, H Wu, Y Cao, H Yu
Applied Physics Letters 97 (16), 2010
902010
Performance enhancement of on-chip inductors with permalloy magnetic rings
W Xu, S Sinha, T Dastagir, H Wu, B Bakkaloglu, DS Gardner, Y Cao, H Yu
IEEE Electron Device Letters 32 (1), 69-71, 2010
642010
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools
K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
632016
Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm
D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ...
2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019
622019
Effect of steroidal fraction of seeds of Abrus precatorius Linn. on rat testis.
S Sinha, RS Mathur
Indian journal of experimental biology 28 (8), 752-756, 1990
521990
Standard cell library design and optimization methodology for ASAP7 PDK
X Xu, N Shah, A Evans, S Sinha, B Cline, G Yeric
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 999 …, 2017
502017
Replacing copper interconnects with graphene at a 7-nm node
NC Wang, S Sinha, B Cline, CD English, G Yeric, E Pop
2017 IEEE International Interconnect Technology Conference (IITC), 1-3, 2017
432017
Improved frequency response of on-chip inductors with patterned magnetic dots
W Xu, S Sinha, F Pan, T Dastagir, Y Cao, H Yu
IEEE electron device letters 31 (3), 207-209, 2010
412010
Design benchmarking to 7nm with FinFET predictive technology models
S Sinha, B Cline, G Yeric, V Chandra, Y Cao
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
392012
Physical design and FinFETs
R Aitken, G Yeric, B Cline, S Sinha, L Shifren, I Iqbal, V Chandra
Proceedings of the 2014 on International symposium on physical design, 65-68, 2014
382014
32-bit processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance
CS Lee, B Cline, S Sinha, G Yeric, HSP Wong
2016 IEEE international electron devices meeting (IEDM), 28.3. 1-28.3. 4, 2016
372016
Compact model of carbon nanotube transistor and interconnect
S Sinha, A Balijepalli, Y Cao
IEEE transactions on electron devices 56 (10), 2232-2242, 2009
362009
Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology
L Shifren, R Aitken, AR Brown, V Chandra, B Cheng, C Riddet, ...
IEEE Transactions on Electron Devices 61 (7), 2271-2277, 2014
322014
Sub-100 μm scale on-chip inductors with CoZrTa for GHz applications
W Xu, H Wu, DS Gardner, S Sinha, T Dastagir, B Bakkaloglu, Y Cao, H Yu
Journal of Applied Physics 109 (7), 2011
322011
The past present and future of design-technology co-optimization
G Yeric, B Cline, S Sinha, D Pietromonaco, V Chandra, R Aitken
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013
292013
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Artículos 1–20