Teerachot Siriburanon
Teerachot Siriburanon
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A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique
W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014
992014
A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration
A Musa, W Deng, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 49 (1), 50-60, 2013
942013
Chaotic modelling and simulation: analysis of chaotic models, attractors and forms
CH Skiadas, C Skiadas
CRC Press, 2008
812008
64-QAM 60-GHz CMOS transceivers for IEEE 802.11 ad/ay
R Wu, R Minami, Y Tsukui, S Kawai, Y Seo, S Sato, K Kimura, S Kondo, ...
IEEE Journal of Solid-State Circuits 52 (11), 2871-2891, 2017
632017
15.1 A 0.0066mm2780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique
W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
622014
A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad
T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ...
IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016
582016
A sub-harmonic injection-locked quadrature frequency synthesizer with frequency calibration scheme for millimeter-wave TDD transceivers
W Deng, T Siriburanon, A Musa, K Okada, A Matsuzawa
IEEE Journal of Solid-State Circuits 48 (7), 1710-1720, 2013
562013
A 0.022mm2970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits
W Deng, A Musa, T Siriburanon, M Miyahara, K Okada, A Matsuzawa
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
492013
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802. 11ay with calibration of LO feedthrough and I/Q imbalance
J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ...
2017 IEEE International Solid-State Circuits Conference (ISSCC), 424-425, 2017
47*2017
A 2.2 GHz-242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture
T Siriburanon, S Kondo, K Kimura, T Ueno, S Kawashima, T Kaneko, ...
IEEE Journal of Solid-State Circuits 51 (6), 1385-1397, 2016
472016
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique
W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
472015
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11 ay
R Wu, S Kawai, Y Seo, N Fajri, K Kimura, S Sato, S Kondo, T Ueno, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 248-249, 2016
422016
A 60-GHz Sub-Sampling Frequency Synthesizer Using Sub-Harmonic Injection-Locked Quadrature Oscillators
T Siriburanon, T Ueno, K Kimura, S Kondo, W Deng, K Okada, ...
312014
A Low-Flicker-Noise 30-GHz Class-F23Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path
Y Hu, T Siriburanon, RB Staszewski
IEEE Journal of Solid-State Circuits 53 (7), 1977-1987, 2018
262018
High-Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits
N Li, K Okada, T Inoue, T Hirano, Q Bu, AT Narayanan, T Siriburanon, ...
IEEE Transactions on Electron Devices 62 (4), 1269-1275, 2015
262015
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular
T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
232015
A 13.2% locking-range divide-by-6, 3.1 mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs
T Siriburanon, W Deng, A Musa, K Okada, A Matsuzawa
2013 Proceedings of the ESSCIRC (ESSCIRC), 403-406, 2013
212013
A mixed-signal control core for a fully integrated semiconductor quantum computer system-on-chip
I Bashir, M Asker, C Cetintepe, D Leipold, A Esmailiyan, H Wang, ...
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
192019
A 0.5-V 1.6-mW 2.4-GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28-nm CMOS
N Pourmousavian, FW Kuo, T Siriburanon, M Babaie, RB Staszewski
IEEE Journal of Solid-State Circuits 53 (9), 2572-2583, 2018
162018
A 0.5 V 1.6 mW 2.4 GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS
FW Kuo, S Pourmousavian, T Siriburanon, R Chen, L Cho, CP Jou, ...
2017 Symposium on VLSI Circuits, C178-C179, 2017
122017
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