Alex Orailoglu
Alex Orailoglu
Professor of Computer Science & Engineering, University of California San Diego
Dirección de correo verificada de cs.ucsd.edu
Título
Citado por
Citado por
Año
Test volume and application time reduction through scan chain concealment
I Bayraktaroglu, A Orailoglu
Proceedings of the 38th Annual Design Automation Conference, 151-155, 2001
2612001
Flow graph representation
A Orailoglu, DD Gajski
Proceedings of the 23rd ACM/IEEE Design Automation Conference, 503-509, 1986
1181986
Architectures for silicon nanoelectronics and beyond
RI Bahar, D Hammerstrom, J Harlow, WH Joyner, C Lau, D Marculescu, ...
Computer 40 (1), 25-33, 2007
1032007
Reducing test application time through test data mutation encoding
S Reda, A Orailoglu
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
922002
Test power reduction through minimization of scan chain transitions
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 166-171, 2002
842002
Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression
I Bayraktaroglu, A Orailoglu
Proceedings. 21st VLSI Test Symposium, 2003., 113-118, 2003
772003
Automatic synthesis of self-recovering VLSI systems
A Orailoglu, R Karri
IEEE Transactions on Computers 45 (2), 131-142, 1996
751996
Test application time and volume compression through seed overlapping
W Rao, I Bayraktaroglu, A Orailoglu
Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451 …, 2003
692003
Concurrent application of compaction and compression for test time and data volume reduction in scan designs
I Bayraktaroglu, A Orailoglu
IEEE Transactions on Computers 52 (11), 1480-1489, 2003
672003
CircularScan: a scan architecture for test cost reduction
B Arslan, A Orailoglu
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
652004
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses
R Ayoub, A Orailoglu
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
622005
Low-power instruction bus encoding for embedded processors
P Petrov, A Orailoglu
IEEE transactions on very large scale integration (VLSI) systems 12 (8), 812-826, 2004
602004
Microarchitectural synthesis of performance-constrained, low-power VLSI designs
L Goodby, A Orailoglu, PM Chau
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994
601994
Microarchitectural synthesis of VLSI designs with high test concurrency
IG Harris, A Orailoglu
Proceedings of the 31st annual Design Automation Conference, 206-211, 1994
601994
Performance analysis and optimization of asynchronous circuits
P Kudva, G Gopalakrishnan, E Brunvand, V Akella
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994
58*1994
A novel scan architecture for power-efficient, rapid test
O Sinanoglu, A Orailoglu
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
552002
Modeling scan chain modifications for scan-in test power minimization
O Sinanoglu, A Orailoglu
ITC, 602-611, 2003
512003
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures
A Orailoglu, R Karri
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (3), 304-311, 1994
501994
Scan power reduction through test data transition frequency analysis
O Sinanoglu, I Bayraktaroglu, A Orailoglu
Proceedings. International Test Conference, 844-850, 2002
492002
Test cost minimization through adaptive test development
M Chen, A Orailoglu
2008 IEEE International Conference on Computer Design, 234-239, 2008
462008
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20