| Template based synthesis for high performance computing M Fujita, Y Kimura, Q Wang 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 8 | 2017 |
| Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs Q Wang, Y Kimura, M Fujita 2017 18th International Symposium on Quality Electronic Design (ISQED), 432-437, 2017 | 3 | 2017 |
| High-level engineering change through programmable datapath and SMT solvers Q Wang, AM Gharehbaghi, T Matsumoto, M Fujita 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 2 | 2019 |
| Automatically adjusting system level designs after RTL/gate-level ECO Q Wang, Y Kimura, M Fujita 2016 IEEE International High Level Design Validation and Test Workshop …, 2016 | 2 | 2016 |
| Communication Aware Compiler for Mesh-Structured Reconfigurable Processors on Single/Multi Chip Y Lu, Q Wang, AM Gharehbaghi, M Fujita IEICE Proceedings Series 61 (5151), 2016 | 1 | 2016 |
| Template-Based Semi-Formal Approach to Robust Equivalence Checking Q Wang, M Fujita Electronics 11 (11), 1691, 2022 | | 2022 |
| High-Level Debugging of Post-Silicon Failures M Fujita, Q Wang, Y Kimura Post-Silicon Validation and Debug, 231-253, 2019 | | 2019 |
| A New Semi-formal Approach to Functional Testing M Fujita, Y Kimura, Q Wang IEEE Workshop on RTL and High Level Testing, 2018 | | 2018 |
| Template-based C Description Generation after ECO at RTL Design Stage Q Wang, Y Kimura, AM Gharehbaghi, M Fujita Technical Report of IEICE, 2017 | | 2017 |
| Mapping Analysis Between RTL/High-Level and Gate-Level Designs with Inductive Invariants on Partial Behaviors M Fujita, Q Wang, Y Kimura IEEE Workshop on RTL and High Level Testing, 2015 | | 2015 |
Masahiro FujitaUniversity of TokyoDirección de correo verificada de ee.t.u-tokyo.ac.jp
Masahiro FujitaUniversity of TokyoDirección de correo verificada de ee.t.u-tokyo.ac.jp