| Enabling sub-5nm CMOS technology scaling thinner and taller! J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ... 2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019 | 86 | 2019 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 82 | 2019 |
| Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ... 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015 | 65 | 2015 |
| Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ... 2019 Symposium on VLSI Technology, T204-T205, 2019 | 59 | 2019 |
| Non-volatile spin wave majority gate at the nanoscale O Zografos, S Dutta, M Manfrini, A Vaysset, B Sorée, A Naeemi, ... AIP Advances 7 (5), 2017 | 37 | 2017 |
| Spintronic majority gates IP Radu, O Zografos, A Vaysset, F Ciubotaru, J Yan, J Swerts, D Radisic, ... 2015 IEEE International Electron Devices Meeting (IEDM), 32.5. 1-32.5. 4, 2015 | 34 | 2015 |
| Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 32 | 2019 |
| Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation S Dutta, O Zografos, S Gurunarayanan, I Radu, B Soree, F Catthoor, ... Scientific reports 7 (1), 17866, 2017 | 30 | 2017 |
| Inversion optimization in majority-inverter graphs E Testa, M Soeken, O Zografos, L Amaru, P Raghavan, R Lauwereins, ... 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 30 | 2016 |
| Exchange-driven magnetic logic O Zografos, M Manfrini, A Vaysset, B Sorée, F Ciubotaru, C Adelmann, ... Scientific reports 7 (1), 12154, 2017 | 25 | 2017 |
| Chain of magnetic tunnel junctions as a spintronic memristor E Raymenants, A Vaysset, D Wan, M Manfrini, O Zografos, O Bultynck, ... Journal of Applied Physics 124 (15), 2018 | 24 | 2018 |
| Inverter propagation and fan-out constraints for beyond-CMOS majority-based technologies E Testa, O Zografos, M Soeken, A Vaysset, M Manfrini, R Lauwereins, ... 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2017 | 22 | 2017 |
| Wave pipelining for majority-based beyond-CMOS technologies O Zografos, A De Meester, E Testa, M Soeken, PE Gaillardon, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 22 | 2017 |
| Confined magnetoelastic waves in thin waveguides F Vanderveken, J Mulkers, J Leliaert, B Van Waeyenberge, B Sorée, ... Physical Review B 103 (5), 054439, 2021 | 20 | 2021 |
| System-level assessment and area evaluation of spin wave logic circuits O Zografos, P Raghavan, L Amaru, B Sorée, R Lauwereins, I Radu, ... Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014 | 20 | 2014 |
| Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network R Chen, M Lofrano, G Mirabelli, G Sisto, S Yang, A Jourdain, F Schleicher, ... 2022 International Electron Devices Meeting (IEDM), 23.4. 1-23.4. 4, 2022 | 18 | 2022 |
| Finite difference magnetoelastic simulator F Vanderveken, J Mulkers, J Leliaert, B Van Waeyenberge, B Sorée, ... Open Research Europe 1, 2021 | 17 | 2021 |
| First experimental demonstration of a scalable linear majority gate based on spin waves F Ciubotaru, G Talmelli, T Devolder, O Zografos, M Heyns, C Adelmann, ... 2018 IEEE International Electron Devices Meeting (IEDM), 36.1. 1-36.1. 4, 2018 | 17 | 2018 |
| Majority logic synthesis L Amarù, E Testa, M Couceiro, O Zografos, G De Micheli, M Soeken 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2018 | 17 | 2018 |
| Wide operating window spin-torque majority gate towards large-scale integration of logic circuits A Vaysset, O Zografos, M Manfrini, D Mocuta, IP Radu AIP Advances 8 (5), 2018 | 17 | 2018 |
Ryckaert JulienimecVerified email at imec.be
