| Design of residue generators and multioperand modular adders using carry-save adders SJ Piestrak IEEE Transactions on Computers 43 (1), 68-77, 1994 | 307 | 1994 |
| Design of residue generators and multioperand modular adders using carry-save adders SJ Piestrak Proc. 10th Symp. on Computer Arithmetic, 100-107, 1991 | 307 | 1991 |
| Design of self-testing checkers for unidirectional error detecting codes SJ Piestrak Scientific Papers of the Inst. of Techn. Cybern. of the Wroclaw Univ. of …, 1995 | 292 | 1995 |
| A high-speed realization of a residue to binary number system converter SJ Piestrak IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1995 | 225 | 1995 |
| Low overhead fault-tolerance technique for dynamically reconfigurable softcore processor HM Pham, S Pillement, SJ Piestrak IEEE Transactions on Computers 62 (6), 1179-1192, 2013 | 78 | 2013 |
| Design of fast self-testing checkers for a class of Berger codes SJ Piestrak IEEE Transactions on Computers, 629-634, 1987 | 63 | 1987 |
| Design of fast self-testing checkers for a class of Berger codes SJ Piestrak Dig. Papers 15th Int. Symp. on Fault-Tolerant Computing (FTCS-15), 418-423, 1985 | 63 | 1985 |
| Exploiting residue number system for power-efficient digital signal processing in embedded processors R Chokshi, KS Berezowski, A Shrivastava, SJ Piestrak Proc. ACM Embedded Systems Week Conf. - CASES, 19-27, 2009 | 58 | 2009 |
| Towards totally self-checking delay-insensitive systems SJ Piestrak, T Nanya Dig. Pap. 25th Int. Symp. on Fault-Tolerant Computing (FTCS-25), 228-237, 1995 | 54 | 1995 |
| Design of high-speed residue-to-binary number system converter based on Chinese Remainder Theorem SJ Piestrak Proc. Int. Conf. on Computer Design: VLSI in Computers & Processors (ICCD'94 …, 1994 | 53 | 1994 |
| Design of Reverse Converters for General RNS Moduli Sets { 2^k, 2^n-1, 2^n+1, 2^{n-1}-1 } and { 2^k, 2^n-1, 2^n+1, 2^{n+1}-1 } (n even) P Patronik, SJ Piestrak IEEE Transactions on Circuits and Systems-I: Regular Papers 61 (6), 1687-1700, 2014 | 44 | 2014 |
| Design of a fault-tolerant coarse-grained reconfigurable architecture: A case study SMAH Jafri, SJ Piestrak, O Sentieys, S Pillement Proc. 11th Int. Symp. on Quality Electronic Design (ISQED), 845-852, 2010 | 40 | 2010 |
| The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes SJ Piestrak Dig. Pap. 20th Int. Symp. on Fault-Tolerant Computing (FTCS-20), 457-464, 1990 | 39 | 1990 |
| Design method of totally self-checking checkers for m-out-of-n codes SJ Piestrak Dig. Pap. 13th Int. Symp. on Fault-Tolerant Computing (FTCS-13), 162-168, 1983 | 39 | 1983 |
| Design of squarers modulo A with low-level pipelining SJ Piestrak IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002 | 36 | 2002 |
| Membership test logic for delay-insensitive codes SJ Piestrak Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems …, 1998 | 35 | 1998 |
| Fast and energy-efficient constant-coefficient FIR filters using residue number system P Patronik, KS Berezowski, SJ Piestrak, J Biernat, A Shrivastava Proc. Int. Symp. on Low Power Electronics and Design (ISLPED), 385-390, 2011 | 30 | 2011 |
| Design of residue multipliers-accumulators using periodicity SJ Piestrak, KS Berezowski Proc. 16th IET Irish Signals and Systems Conference (ISSC 2008), 380-385, 2008 | 28 | 2008 |
| Efficient Hamming weight comparators of binary vectors SJ Piestrak Electronics Letters 43 (11), 611-612, 2007 | 28 | 2007 |
| Error recovery technique for coarse-grained reconfigurable architectures MM Azeem, SJ Piestrak, O Sentieys, S Pillement Proc. 14th IEEE Symp. on Design and Diagnostics of Electronic Circuits …, 2011 | 27 | 2011 |
Piotr PatronikPolitechnika WrocławskaDirección de correo verificada de pwr.edu.pl
