| Schmitt trigger based SRAM cell for ultralow power operation-a CNFET based approach V Srinivasan, RV Venkatraman Procedia Engineering 64, 115-124, 2013 | 45 | 2013 |
| Under 100-cycle thread migration latency in a single-isa heterogeneous multi-core processor E Forbes, Z Zhang, R Widialaksono, B Dwiel, RBR Chowdhury, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-1, 2015 | 14 | 2015 |
| Scoc ip cores for custom built supercomputing nodes V Nagarajan, R Hariharan, V Srinivasan, RS Kannan, P Thinakaran, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 255-260, 2012 | 12 | 2012 |
| Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores V Nagarajan, K Lakshminarasimhan, A Sridhar, P Thinakaran, ... 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 200-205, 2013 | 10 | 2013 |
| Compilation accelerator on silicon V Nagarajan, V Srinivasan, R Kannan, P Thinakaran, R Hariharan, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 267-272, 2012 | 10 | 2012 |
| Slipstream processors revisited: Exploiting branch sets V Srinivasan, RBR Chowdhury, E Rotenberg 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 9 | 2020 |
| H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor V Srinivasan, RBR Chowdhury, E Forbes, R Widialaksono, Z Zhang, ... 2017 IEEE International Conference on Computer Design (ICCD), 145-152, 2017 | 8 | 2017 |
| Experiences with two fabscalar-based chips E Forbes, RBR Chowdhury, B Dwiel, A Kannepalli, V Srinivasan, Z Zhang, ... 6th Workshop on Architectural Research Prototyping (WARP-6), 2015 | 8 | 2015 |
| Phase II Implementation and Verification of the H3 Processor. V Srinivasan | 5 | 2015 |
| SCOC IP Cores for Custom Built Supercomputing Nodes. N Venkateswaran, R Hariharan, V Srinivasan, RS Kannan, P Thinakaran, ... ISVLSI, 255-260, 2012 | 4 | 2012 |
| ProcediaEngineering V Srinivasan, R VarshadVenkatraman, KK Senthilkumar Volume 64, 115-124, 2013 | 3 | 2013 |
| Slipstream Processors Revisited: Exploiting Branch Sets V Srinivasan North Carolina State University, 2019 | 2 | 2019 |
| Branch target filtering based on memory region access count VS John Kalamatianos, Adithya Yalavarti, Varun Agrawal, Subhankar Pal US Patent 11,550,588, 2023 | | 2023 |
| FILTERED BRANCH PREDICTION STRUCTURES OF A PROCESSOR VS John KALAMATIANOS, Adithya YALAVARTI, Varun AGRAWAL, Subhankar PAL US Patent 20,200,065,106, 2020 | | 2020 |
| Silicon Operating System for Large Scale Heterogeneous Cores and its FPGA Implementation V Srinivasan | | 2012 |
Rangeen Basu Roy ChowdhuryCPU Performance Architect @ Arm IncDirección de correo verificada de arm.com
