Batch active learning at scale G Citovsky, G DeSalvo, C Gentile, L Karydas, A Rajagopalan, ... Advances in Neural Information Processing Systems 34, 11933-11944, 2021 | 157 | 2021 |
Scaling hierarchical agglomerative clustering to billion-sized datasets B Sumengen, A Rajagopalan, G Citovsky, D Simcha, O Bachem, P Mitra, ... arXiv preprint arXiv:2105.11653, 2021 | 20 | 2021 |
Online hierarchical clustering approximations AK Menon, A Rajagopalan, B Sumengen, G Citovsky, Q Cao, S Kumar arXiv preprint arXiv:1909.09667, 2019 | 17 | 2019 |
Hierarchical clustering of data streams: Scalable algorithms and approximation guarantees A Rajagopalan, F Vitale, D Vainstein, G Citovsky, CM Procopiuc, ... International conference on machine learning, 8799-8809, 2021 | 11 | 2021 |
Hierarchical clustering via sketches and hierarchical correlation clustering D Vainstein, V Chatziafratis, G Citovsky, A Rajagopalan, M Mahdian, ... International Conference on Artificial Intelligence and Statistics, 559-567, 2021 | 10 | 2021 |
Flattening a hierarchical clustering through active learning F Vitale, A Rajagopalan, C Gentile Advances in Neural Information Processing Systems 32, 2019 | 8* | 2019 |
A 5nm 3.4 GHz tri-gear ARMv9 CPU subsystem in a fully integrated 5G flagship mobile SoC A Nayak, HC Chen, H Mair, R Lagerquist, T Chen, A Rajagopalan, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 50-52, 2022 | 6 | 2022 |
Outlier eigenvalue fluctuations of perturbed iid matrices AB Rajagopalan University of California, Los Angeles, 2015 | 6 | 2015 |
4.1 A 7nm 5G Mobile SoC Featuring a 3.0 GHz Tri-Gear Application Processor Subsystem H Chen, R Lagerquist, A Nayak, H Mair, G Manoharan, E Wang, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 54-56, 2021 | 5 | 2021 |
A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. In 2016 IEEE International Solid-State Circuits … HT Mair, G Gammie, A Wang, R Lagerquist, CJ Chung, S Gururajarao, ... IEEE, 2016 | 3 | 2016 |
Circuit and method to measure simulation to silicon timing correlation AK Nayak, HT Mair, A Varma, A Rajagopalan US Patent 11,835,580, 2023 | | 2023 |
Batch Active Learning at Scale A Rostamizadeh, C Gentile, G DeSalvo, G Citovsky, L Karydas, S Kumar | | 2021 |