| An assertion-based verification methodology for system-level design AM Gharehbaghi, BH Yaran, S Hessabi, M Goudarzi Computers & Electrical Engineering 33 (4), 269-284, 2007 | 33* | 2007 |
| Transaction-based debugging of system-on-chips with patterns AM Gharehbaghi, M Fujita 2009 IEEE International Conference on Computer Design, 186-192, 2009 | 32 | 2009 |
| Intermediate Format Standardization: Ambiguities, Deficiencies, Portability issues, Documentation and Improvements MH Reshadi, AM Gharehbaghi, Z Navabi HDLCon2000, 2000 | 31* | 2000 |
| Transaction-based post-silicon debug of many-core system-on-chips AM Gharehbaghi, M Fujita Thirteenth International Symposium on Quality Electronic Design (ISQED), 702-708, 2012 | 21 | 2012 |
| Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme H Sun, Z Cheng, AM Gharehbaghi, S Kimura, M Fujita IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1517-1530, 2019 | 18 | 2019 |
| Pipelined microprocessors optimization and debugging B Alizadeh, AM Gharehbaghi, M Fujita International Symposium on Applied Reconfigurable Computing, 435-444, 2010 | 14 | 2010 |
| An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults P Wang, CJ Moore, AM Gharehbaghi, M Fujita IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 1063-1074, 2018 | 11* | 2018 |
| A new approach for debugging logic circuits without explicitly debugging their functionality AM Gharehbaghi, M Fujita 2016 IEEE 25th Asian Test Symposium (ATS), 31-36, 2016 | 11 | 2016 |
| Debugging processors with advanced features by reprogramming LUTs on FPGA S Jo, AM Gharehbaghi, T Matsumoto, M Fujita 2013 International Conference on Field-Programmable Technology (FPT), 50-57, 2013 | 7 | 2013 |
| System-Level Assertion-Based Performance Verification for Embedded Systems H Hatefi-Ardakani, AM Gharehbaghi, S Hessabi Advances in Computer Science and Engineering 6, 243-250, 2009 | 7* | 2009 |
| A new approach for selecting inputs of logic functions during debug AM Gharehbaghi, M Fujita 2017 18th International Symposium on Quality Electronic Design (ISQED), 166-173, 2017 | 6 | 2017 |
| Trace signal selection methods for post silicon debugging S Choudhary, AM Gharehbaghi, T Matsumoto, M Fujita 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 6 | 2015 |
| Formal verification guided automatic design error diagnosis and correction of complex processors AM Gharehbaghi, M Fujita 2011 IEEE International High Level Design Validation and Test Workshop, 121-127, 2011 | 6 | 2011 |
| Global transaction ordering in network-on-chips for post-silicon validation AM Gharehbaghi, M Fujita 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 6 | 2011 |
| Assertion-based debug infrastructure for SoC designs AM Gharehbaghi, M Babagoli, S Hessabi 2007 Internatonal Conference on Microelectronics, 137-140, 2007 | 6 | 2007 |
| Error model free automatic design error correction of complex processors using formal methods AM Gharehbaghi, M Fujita Asian Test Symposium (ATS), 2012 IEEE 21st, 143-148, 2012 | 5 | 2012 |
| Post Silicon Debugging of Electrical Bugs Using Trace Buffers K Iwata, AM Gharehbaghi, MB Tahoori, M Fujita 2017 IEEE 26th Asian Test Symposium (ATS), 189-194, 2017 | 4 | 2017 |
| Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model AM Gharehbaghi, M Fujita IEICE TRANSACTIONS on Information and Systems 97 (4), 852-863, 2014 | 4 | 2014 |
| Specification and formal verification of power gating in processors AM Gharehbaghi, M Fujita Fifteenth International Symposium on Quality Electronic Design, 604-610, 2014 | 4 | 2014 |
| An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults P Wang, AM Gharehbaghi, M Fujita 2019 IEEE 37th VLSI Test Symposium (VTS), 1-6, 2019 | 3 | 2019 |
Masahiro FujitaUniversity of TokyoDirección de correo verificada de ee.t.u-tokyo.ac.jp
