Saeed Shamshiri

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Kwang-Ting (Tim) ChengChair Professor of ECE and CSE, HKUSTDirección de correo verificada de ust.hk
Zainalabedin NavabiProfessor of Electrical and Computer Engineering, University of TehranDirección de correo verificada de ut.ac.ir
Hadi EsmaeilzadehAssociate Professor; Computer Science and Engineering; University of California, San DiegoDirección de correo verificada de eng.ucsd.edu
Amirali GhofraniHardware engineer, GoogleDirección de correo verificada de google.com
Peter LishernessUniversity of California, Santa Barbara Dirección de correo verificada de ece.ucsb.edu
Ritesh ParikhIntelDirección de correo verificada de intel.com
Andrew DeOrioUniversity of MichiganDirección de correo verificada de umich.edu
Valeria BertaccoProfessor, Computer Science and Engineering, University of MichiganDirección de correo verificada de umich.edu
Bijan AlizadehAssociate Professor, University of TehranDirección de correo verificada de ut.ac.ir
Pejman Lotfi-KamranAssociate Professor of Computer Science, IPMDirección de correo verificada de ipm.ir
Ashkan SobhaniPhD Electrical and Computer Engineering, University of OttawaDirección de correo verificada de uottawa.ca
Eiman EbrahimiNVIDIA ResearchDirección de correo verificada de nvidia.com
Ardavan PedramStanford UniversityDirección de correo verificada de stanford.edu
Hosein MahjoubiRobotics Laboratory, ECE Department, University of California at Santa BarbaraDirección de correo verificada de ece.ucsb.edu
Caro LucasUniversity of Tehran
Kia BazarganAssociate Professor of ECE, University of MinnesotaDirección de correo verificada de umn.edu

Saeed Shamshiri

University of California, Santa Barbara

Dirección de correo verificada de umail.ucsb.edu - Página principal

Design for Test Computer Architecture Verification


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
End-to-end error correction and online diagnosis for on-chip networks S Shamshiri, A Ghofrani, KT Cheng 2011 IEEE International Test Conference, 1-10, 2011	85	2011
Comprehensive online defect diagnosis in on-chip networks A Ghofrani, R Parikh, S Shamshiri, A DeOrio, KT Cheng, V Bertacco 2012 IEEE 30th VLSI Test Symposium (VTS), 44-49, 2012	53	2012
A cost analysis framework for multi-core systems with spares S Shamshiri, P Lisherness, SJ Pan, KT Cheng 2008 IEEE International Test Conference, 1-8, 2008	42	2008
Modeling yield, cost, and quality of a spare-enhanced multicore chip S Shamshiri, KT Cheng IEEE Transactions on Computers 60 (9), 1246-1259, 2011	37	2011
Yield and cost analysis of a reliable NoC S Shamshiri, KT Cheng 2009 27th IEEE VLSI Test Symposium, 173-178, 2009	37	2009
Error-locality-aware linear coding to correct multi-bit upsets in SRAMs S Shamshiri, KT Cheng 2010 IEEE International Test Conference, 1-10, 2010	33	2010
Instruction-level test methodology for CPU core self-testing S Shamshiri, H Esmaeilzadeh, Z Navabi ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (4 …, 2005	17	2005
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy S Shamshiri, KT Cheng 2010 28th VLSI Test Symposium (VTS), 194-199, 2010	9	2010
Test instruction set (TIS) for high level self-testing of CPU cores S Shamshiri, H Esmaeilzadeh, Z Navabi 13th Asian Test Symposium, 158-163, 2004	8	2004
Hardware accelerator IP-core for wireless 802.16 MAC H Holisaz, S Shamshiri, F Baharvand, SM Fakhraie 2006 IFIP International Conference on Wireless and Optical Communications …, 2006	6	2006
Instruction level test methodology for CPU core software-based self-testing S Shamshiri, H Esmaeilzadeh, Z Navabi Proceedings. Ninth IEEE International High-Level Design Validation and Test …, 2004	6	2004
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems Y Zheng, P Lisherness, S Shamshiri, A Ghofrani, S Yang, KTT Cheng 17th Asia and South Pacific Design Automation Conference, 615-620, 2012	5	2012
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing H Esmaeilzadeh, S Shamshiri, P Saeedi, Z Navabi 14th Asian Test Symposium (ATS'05), 236-241, 2005	5	2005
Binary Taylor diagrams: An efficient implementation of Taylor expansion diagrams A Hooshmand, S Shamshiri, M Alisafaee, P Lotfi-Kamran, M Naderi, ... 2005 IEEE International Symposium on Circuits and Systems, 424-427, 2005	5	2005
Test instruction set (TIS): An instruction level CPU core self-testing method S Shamshiri, H Esmaeilzadeh, M Alisafaee, P Lotfikamran, Z Navabi Proceedings of 9th IEEE European Test Symposium (ETS’04), 15-16, 2004	4	2004
Parallel alias reduction for MP3 decoding S Shamshiri, SM Fakhraie Proceedings. The 16th International Conference on Microelectronics, 2004 …, 2004	3	2004
Scan Chain Bypass by Use of Skip Path F Fakhrieh, S Shamshiri, A Pedram, A Sobhani, Z Navabi 2005 International Conference on Microelectronics, 82-85, 2005	1	2005
Interleaved scan-cell architecture for low power test H Esmaeilzadeh, S Shamshiri, P Saeedi, E Ebrahimi, Z Navabi IEEE 5th Workshop on Register Transfer level Test (WRTLT'04), 123-128, 2004	1	2004
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips S Shamshiri University of California, Santa Barbara, 2011		2011
GENETIC-ALGORITHM MEMORY MINIMISATION FOR DESIGNING RECONFIGURABLE IP ADDRESS LOOKUP ENGINE S Shamshiri, SM Fakhraie International Journal of Computational Intelligence and Applications 5 (01 …, 2005		2005

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