Saeed Shamshiri
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End-to-end error correction and online diagnosis for on-chip networks
S Shamshiri, A Ghofrani, KT Cheng
2011 IEEE International Test Conference, 1-10, 2011
852011
Comprehensive online defect diagnosis in on-chip networks
A Ghofrani, R Parikh, S Shamshiri, A DeOrio, KT Cheng, V Bertacco
2012 IEEE 30th VLSI Test Symposium (VTS), 44-49, 2012
532012
A cost analysis framework for multi-core systems with spares
S Shamshiri, P Lisherness, SJ Pan, KT Cheng
2008 IEEE International Test Conference, 1-8, 2008
422008
Modeling yield, cost, and quality of a spare-enhanced multicore chip
S Shamshiri, KT Cheng
IEEE Transactions on Computers 60 (9), 1246-1259, 2011
372011
Yield and cost analysis of a reliable NoC
S Shamshiri, KT Cheng
2009 27th IEEE VLSI Test Symposium, 173-178, 2009
372009
Error-locality-aware linear coding to correct multi-bit upsets in SRAMs
S Shamshiri, KT Cheng
2010 IEEE International Test Conference, 1-10, 2010
332010
Instruction-level test methodology for CPU core self-testing
S Shamshiri, H Esmaeilzadeh, Z Navabi
ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (4 …, 2005
172005
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy
S Shamshiri, KT Cheng
2010 28th VLSI Test Symposium (VTS), 194-199, 2010
92010
Test instruction set (TIS) for high level self-testing of CPU cores
S Shamshiri, H Esmaeilzadeh, Z Navabi
13th Asian Test Symposium, 158-163, 2004
82004
Hardware accelerator IP-core for wireless 802.16 MAC
H Holisaz, S Shamshiri, F Baharvand, SM Fakhraie
2006 IFIP International Conference on Wireless and Optical Communications …, 2006
62006
Instruction level test methodology for CPU core software-based self-testing
S Shamshiri, H Esmaeilzadeh, Z Navabi
Proceedings. Ninth IEEE International High-Level Design Validation and Test …, 2004
62004
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Y Zheng, P Lisherness, S Shamshiri, A Ghofrani, S Yang, KTT Cheng
17th Asia and South Pacific Design Automation Conference, 615-620, 2012
52012
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing
H Esmaeilzadeh, S Shamshiri, P Saeedi, Z Navabi
14th Asian Test Symposium (ATS'05), 236-241, 2005
52005
Binary Taylor diagrams: An efficient implementation of Taylor expansion diagrams
A Hooshmand, S Shamshiri, M Alisafaee, P Lotfi-Kamran, M Naderi, ...
2005 IEEE International Symposium on Circuits and Systems, 424-427, 2005
52005
Test instruction set (TIS): An instruction level CPU core self-testing method
S Shamshiri, H Esmaeilzadeh, M Alisafaee, P Lotfikamran, Z Navabi
Proceedings of 9th IEEE European Test Symposium (ETS’04), 15-16, 2004
42004
Parallel alias reduction for MP3 decoding
S Shamshiri, SM Fakhraie
Proceedings. The 16th International Conference on Microelectronics, 2004 …, 2004
32004
Scan Chain Bypass by Use of Skip Path
F Fakhrieh, S Shamshiri, A Pedram, A Sobhani, Z Navabi
2005 International Conference on Microelectronics, 82-85, 2005
12005
Interleaved scan-cell architecture for low power test
H Esmaeilzadeh, S Shamshiri, P Saeedi, E Ebrahimi, Z Navabi
IEEE 5th Workshop on Register Transfer level Test (WRTLT'04), 123-128, 2004
12004
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
S Shamshiri
University of California, Santa Barbara, 2011
2011
GENETIC-ALGORITHM MEMORY MINIMISATION FOR DESIGNING RECONFIGURABLE IP ADDRESS LOOKUP ENGINE
S Shamshiri, SM Fakhraie
International Journal of Computational Intelligence and Applications 5 (01 …, 2005
2005
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Artículos 1–20