| The design and analysis of dual-delay-path ring oscillators ZZ Chen, TC Lee IEEE Transactions on Circuits and Systems I: Regular Papers 58 (3), 470-478, 2010 | 103 | 2010 |
| A 0.56 THz phase-locked frequency synthesizer in 65 nm CMOS technology Y Zhao, ZZ Chen, Y Du, Y Li, R Al Hadi, G Virbila, Y Xu, Y Kim, A Tang, ... IEEE Journal of Solid-State Circuits 51 (12), 3005-3019, 2016 | 74 | 2016 |
| 14.9 Sub-sampling all-digital fractional-N frequency synthesizer with− 111dBc/Hz in-band phase noise and an FOM of− 242dB ZZ Chen, YH Wang, J Shin, Y Zhao, SA Mirhaj, YC Kuan, HN Chen, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 64 | 2015 |
| A 16-Gb/s 14.7-mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16/256-QAM and channel response detection Y Du, WH Cho, PT Huang, Y Li, CH Wong, J Du, Y Kim, B Hu, L Du, C Liu, ... IEEE Journal of Solid-State Circuits 52 (4), 1111-1122, 2016 | 48 | 2016 |
| 2.1 An integrated 0.56 THz frequency synthesizer with 21GHz locking range and− 74dBc/Hz phase noise at 1MHz offset in 65nm CMOS Y Zhao, ZZ Chen, G Virbila, Y Xu, R Al Hadi, Y Kim, A Tang, T Reck, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 36-37, 2016 | 27 | 2016 |
| The study of a dual-mode ring oscillator ZZ Chen, TC Lee IEEE Transactions on Circuits and Systems II: Express Briefs 58 (4), 210-214, 2011 | 23 | 2011 |
| 6.7 A 2.3 mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices L Du, Y Zhang, F Hsiao, A Tang, Y Zhao, Y Li, ZZ Chen, L Huang, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 17 | 2015 |
| Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers ZZ Chen, Y Li, YC Kuan, B Hu, CH Wong, MCF Chang 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 16 | 2016 |
| CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systems A Tang, MCF Chang, G Chattopadhyay, Z Chen, T Reck, H Schone, ... Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 15 | 2014 |
| A wide-band 65nm CMOS 28–34 GHz synthesizer module enabling low power heterodyne spectrometers for planetary exploration ZZ Chen, A Tang, Y Kim, G Virbila, T Reck, JF Yei, Y Du, ... 2015 IEEE MTT-S International Microwave Symposium, 1-3, 2015 | 14 | 2015 |
| DPLL for phase noise cancellation in ring oscillator-based quadrature receivers ZZ Chen, YC Kuan, Y Li, B Hu, CH Wong, MCF Chang IEEE Journal of Solid-State Circuits 52 (4), 1134-1143, 2017 | 8 | 2017 |
| An 8-bit compressive sensing ADC with 4-GS/s equivalent speed utilizing self-timed pipeline SAR-binary-search B Hu, F Ren, ZZ Chen, X Jiang, MCF Chang IEEE Transactions on Circuits and Systems II: Express Briefs 63 (10), 934-938, 2016 | 6 | 2016 |
| An all-digital de-skew clock generator for arbitrary wide range delay K Fong, YC Hung, ZZ Chen, TC Lee 2010 IEEE Asia Pacific Conference on Circuits and Systems, 112-115, 2010 | 5 | 2010 |
| 9‐bit time–digital‐converter‐assisted compressive‐sensing analogue–digital‐converter with 4 GS/s equivalent speed B Hu, F Ren, ZZ Chen, X Jiang, MCF Chang Electronics Letters 52 (6), 430-432, 2016 | 3 | 2016 |
| A multiphase compensation method with dynamic element matching technique in Σ-∆ fractional-N frequency synthesizers ZZ Chen, TC Lee Journal of semiconductor technology and science 8 (3), 179-192, 2008 | 2 | 2008 |
| The Reduction and Cancellation of Phase Noise in Digital Frequency Synthesizers and Quadrature Receivers ZZ Chen UCLA, 2016 | | 2016 |
