Timothy M. Jones
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The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
HELIX: Automatic parallelization of irregular programs for chip multiprocessing
S Campanoni, T Jones, G Holloway, VJ Reddi, GY Wei, D Brooks
Proceedings of the Tenth International Symposium on Code Generation and …, 2012
Microarchitectural design space exploration using an architecture-centric approach
C Dubach, T Jones, M O'Boyle
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
A predictive model for dynamic microarchitectural adaptivity control
C Dubach, TM Jones, EV Bonilla, MFP O'Boyle
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 485-496, 2010
Muontrap: Preventing cross-domain spectre-like attacks by capturing speculative state
S Ainsworth, TM Jones
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
Graph prefetching using data structure knowledge
S Ainsworth, TM Jones
Proceedings of the 2016 International Conference on Supercomputing, 1-11, 2016
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
KT Sundararajan, V Porpodas, TM Jones, NP Topham, B Franke
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
Cherivoke: Characterising pointer revocation using cheri capabilities for temporal memory safety
H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Portable compiler optimisation across embedded programs and microarchitectures using machine learning
C Dubach, TM Jones, EV Bonilla, G Fursin, MFP O'Boyle
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
An event-triggered programmable prefetcher for irregular workloads
S Ainsworth, TM Jones
ACM Sigplan Notices 53 (2), 578-592, 2018
Cornucopia: Temporal safety for CHERI heaps
NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ...
2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
S Campanoni, K Brownell, S Kanev, TM Jones, GY Wei, D Brooks
ACM SIGARCH Computer Architecture News 42 (3), 217-228, 2014
Software prefetching for indirect memory accesses
S Ainsworth, TM Jones
2017 IEEE/ACM International Symposium on Code Generation and Optimization …, 2017
MarkUs: Drop-in use-after-free prevention for low-level languages
S Ainsworth, TM Jones
2020 IEEE Symposium on Security and Privacy (SP), 578-591, 2020
PSLP: Padded SLP automatic vectorization
V Porpodas, A Magni, TM Jones
2015 IEEE/ACM International Symposium on Code Generation and Optimization …, 2015
Smart cache: A self adaptive cache architecture for energy efficiency
KT Sundararajan, TM Jones, N Topham
2011 International Conference on Embedded Computer Systems: Architectures …, 2011
Throttling automatic vectorization: When less is more
V Porpodas, TM Jones
2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015
Compiler directed early register release
TM Jones, MFR O'Boyle, J Abella, A González, O Ergin
14th International Conference on Parallel Architectures and Compilation …, 2005
Evaluating the effects of compiler optimisations on AVF
TM Jones, MFP O’Boyle, O Ergin
Workshop on interaction between compilers and computer architecture …, 2008
HELIX: Making the extraction of thread-level parallelism mainstream
S Campanoni, TM Jones, G Holloway, GY Wei, D Brooks
IEEE Micro 32 (4), 8-18, 2012
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