| Heterogeneous integration at fine pitch (≤ 10 µm) using thermal compression bonding AA Bajwa, SC Jangam, S Pal, N Marathe, T Bai, T Fukushima, M Goorsky, ... 2017 IEEE 67th electronic components and technology conference (ECTC), 1276-1284, 2017 | 100 | 2017 |
| Optimizing multi-GPU parallelization strategies for deep learning training S Pal, E Ebrahimi, A Zulfiqar, Y Fu, V Zhang, S Migacz, D Nellans, ... Ieee Micro 39 (5), 91-101, 2019 | 59 | 2019 |
| Latency, bandwidth and power benefits of the superchips integration scheme SC Jangam, S Pal, A Bajwa, S Pamarti, P Gupta, SS Iyer 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 86-94, 2017 | 53 | 2017 |
| Architecting waferscale processors-a GPU case study S Pal, D Petrisko, M Tomei, P Gupta, SS Iyer, R Kumar 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 45 | 2019 |
| A case for packageless processors S Pal, D Petrisko, AA Bajwa, P Gupta, SS Iyer, R Kumar 2018 IEEE international symposium on high performance computer architecture …, 2018 | 33 | 2018 |
| Design space exploration for chiplet-assembly-based processors S Pal, D Petrisko, R Kumar, P Gupta IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4 …, 2020 | 26 | 2020 |
| Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (< 6 µm) and Reliable Flexible Cu-Based … A Hanna, A Alam, T Fukushima, S Moran, W Whitehead, SC Jangam, ... 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 1505-1511, 2018 | 26 | 2018 |
| “FlexTrate^ TM”—Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP T Fukushima, A Alam, Z Wan, SC Jangam, S Pal, G Ezhilarasu, A Bajwa, ... 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 649-654, 2017 | 26 | 2017 |
| Demonstration of a heterogeneously integrated system-on-wafer (SoW) assembly AA Bajwa, SC Jangam, S Pal, B Vaisband, R Irwin, M Goorsky, SS Iyer 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 1926-1930, 2018 | 21 | 2018 |
| Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing S Wang, S Pal, T Li, A Pan, C Grezes, P Khalili-Amiri, KL Wang, P Gupta 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2017 | 20 | 2017 |
| Designing a 2048-chiplet, 14336-core waferscale processor S Pal, J Liu, I Alam, N Cebry, H Suhail, S Bu, SS Iyer, S Pamarti, R Kumar, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 1183-1188, 2021 | 19 | 2021 |
| Cable length minimisation in long-reach-PON planning for sparsely populated areas S Pal, C Zukowski, A Nag, DB Payne, M Ruffini 2014 International Conference on Optical Network Design and Modeling, 234-239, 2014 | 10 | 2014 |
| FPGA implementation of stream cipher using Toeplitz Hash function S Pal, KKS Pandian, KC Ray 2014 International Conference on Advances in Computing, Communications and …, 2014 | 9 | 2014 |
| Compression with multi-ECC: Enhanced error resiliency for magnetic memories I Alam, S Pal, P Gupta Proceedings of the International Symposium on Memory Systems, 85-100, 2019 | 6 | 2019 |
| Chiplets: How Small is too Small? A Graening, S Pal, P Gupta 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 4 | 2023 |
| I/o architecture, substrate design, and bonding process for a heterogeneous dielet-assembly based waferscale processor S Pal, I Alam, K Sahoo, H Suhail, R Kumar, S Pamarti, P Gupta, SS Iyer 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 298-303, 2021 | 4 | 2021 |
| Flexible connectors and PCB segmentation for signaling and power delivery in wafer-scale systems R Irwin, K Sahoo, S Pal, SS Iyer 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 507-513, 2021 | 4 | 2021 |
| Pathfinding for 2.5 D interconnect technologies S Pal, P Gupta Proceedings of the Workshop on System-Level Interconnect: Problems and …, 2020 | 4 | 2020 |
| Copper to gold thermal compression bonding in heterogenous wafer-scale systems K Sahoo, S Pal, N Shakoorzadeh, YT Yang, SS Iyer 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 487-493, 2021 | 3 | 2021 |
| Supervia: Relieving Routing Congestion usingDouble-height Vias S Pal | 3 | 2017 |
SUBRAMANIAN S. IYERUniversity of California at Los Angeles,Dirección de correo verificada de g.ucla.edu
