| Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime F Jazaeri, L Barbut, A Koukab, JM Sallese Solid-State Electronics 82, 103-110, 2013 | 150 | 2013 |
| Step toward robust and reliable amorphous polymer field-effect transistors and logic functions made by the use of roll to roll compatible printing processes JM Verilhac, M Benwadih, AL Seiler, S Jacob, C Bory, J Bablet, ... Organic Electronics 11 (3), 456-462, 2010 | 81 | 2010 |
| A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs JM Sallese, F Jazaeri, L Barbut, N Chevillon, C Lallement IEEE Transactions on Electron Devices, 1-1, 2013 | 54 | 2013 |
| Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel F Jazaeri, L Barbut, JM Sallese IEEE transactions on electron devices 60 (7), 2120-2127, 2013 | 54 | 2013 |
| Trans-capacitance modeling in junctionless gate-all-around nanowire FETs F Jazaeri, L Barbut, JM Sallese Solid-State Electronics 96, 34-37, 2014 | 31 | 2014 |
| Trans-capacitance modeling in junctionless symmetric double-gate MOSFETs F Jazaeri, L Barbut, JM Sallese IEEE Trans. Electron Devices 60 (12), 4034-4040, 2013 | 31 | 2013 |
| Generalized charge-based model of double-gate junctionless FETs, including inversion F Jazaeri, L Barbut, JM Sallese IEEE Transactions on Electron Devices 61 (10), 3553-3557, 2014 | 28 | 2014 |
| Transient off-current in junctionless FETs L Barbut, F Jazaeri, D Bouvet, JM Sallese IEEE transactions on electron devices 60 (6), 2080-2083, 2013 | 28 | 2013 |
| Modeling asymmetric operation in double-gate junctionless FETs by means of symmetric devices F Jazaeri, L Barbut, JM Sallese IEEE Transactions on Electron Devices 61 (12), 3962-3970, 2014 | 27 | 2014 |
| Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices L Barbut, F Jazaeri, D Bouvet, JM Sallese IEEE Transactions on Electron Devices, 2014 | 10 | 2014 |
| Towards circuit design using VeSFETs M Pastre, F Krummenacher, L Barbut, JM Sallese, M Kayal Proceedings of the 18th International Conference Mixed Design of Integrated …, 2011 | 9 | 2011 |
| Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology L Barbut, D Bouvet, JM Sallese CAS 2011 Proceedings (2011 International Semiconductor Conference) 2, 325-328, 2011 | 7 | 2011 |
| Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs L Barbut, F Jazaeri, D Bouvet, JM Sallese International Journal of Microelectronics and Computer Science 4 (3), 103-109, 2013 | 5 | 2013 |
| Heavily doped junctionless vertical slit FETs with slit width Below 20 nm L Barbut, F Jazaeri, D Bouvet, JM Sallese Proceedings of the 20th International Conference Mixed Design of Integrated …, 2013 | 5 | 2013 |
| Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors L Barbut, F Jazaeri, D Bouvet, JM Sallese Mixed Design of Integrated Circuits & Systems, 2013 MIXDES" 13. MIXDES-20th …, 2013 | 5 | 2013 |
| Junctionless Transistors: Challenges and Opportunities in Fabrication and Characterization L Barbut EPFL, 2014 | | 2014 |
Jean-Michel SalleseSenior scientist - Ecole polytechnique Federale de LausanneDirección de correo verificada de epfl.ch
