Bart Swinnen
Bart Swinnen
Afiliación desconocida
Dirección de correo verificada de imec.be
Título
Citado por
Citado por
Año
The phenotypic variability of amyotrophic lateral sclerosis
B Swinnen, W Robberecht
Nature Reviews Neurology 10 (11), 661, 2014
3502014
3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias
B Swinnen, W Ruythooren, P De Moor, L Bogaerts, L Carbonell, ...
2006 International Electron Devices Meeting, 1-4, 2006
2252006
3-D technology assessment: Path-finding the technology/design sweet-spot
P Marchal, B Bougard, G Katti, M Stucchi, W Dehaene, A Papanikolaou, ...
Proceedings of the IEEE 97 (1), 96-107, 2009
1642009
3D stacked IC demonstration using a through silicon via first approach
J Van Olmen, A Mercha, G Katti, C Huyghebaert, J Van Aelst, E Seppala, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
1552008
Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance
A Mercha, G Van der Plas, V Moroz, I De Wolf, P Asimakopoulos, N Minas, ...
2010 International Electron Devices Meeting, 2.2. 1-2.2. 4, 2010
1292010
Through-silicon via and die stacking technologies for microsystems-integration
E Beyne, P De Moor, W Ruythooren, R Labie, A Jourdain, H Tilmans, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
1162008
Impact of 3D design choices on manufacturing cost
D Velenis, M Stucchi, EJ Marinissen, B Swinnen, E Beyne
2009 IEEE International Conference on 3D System Integration, 1-5, 2009
1072009
Mechanical reliability of Au and Cu wire bonds to Al, Ni/Au and Ni/Pd/Au capped Cu bond pads
P Ratchev, S Stoukatch, B Swinnen
Microelectronics Reliability 46 (8), 1315-1325, 2006
952006
Via first plus via last technique for IC interconnects
K Kaskoun, S Gu, B Swinnen
US Patent 7,939,926, 2011
772011
3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding
G Katti, A Mercha, J Van Olmen, C Huyghebaert, A Jourdain, M Stucchi, ...
2009 IEEE international electron devices meeting (IEDM), 1-4, 2009
722009
Method for chip singulation
E Beyne, B Swinnen, S Vanhaelemeersch
US Patent 7,566,634, 2009
702009
Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-Raman spectroscopy
C Okoro, Y Yang, B Vandevelde, B Swinnen, D Vandepitte, B Verlinden, ...
2008 International Interconnect Technology Conference, 16-18, 2008
692008
Scalable through silicon via with polymer deep trench isolation for 3D wafer level packaging
DS Tezcan, F Duval, H Philipsen, O Luhn, P Soussan, B Swinnen
2009 59th Electronic Components and Technology Conference, 1159-1164, 2009
602009
Simultaneous Cu-Cu and compliant dielectric bonding for 3D stacking of ICs
A Jourdain, S Stoukatch, P De Moor, W Ruythooren, S Pargfrieder, ...
2007 IEEE International Interconnect Technology Conferencee, 207-209, 2007
602007
Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
A Jourdain, T Buisson, A Phommahaxay, A Redolfi, S Thangaraju, ...
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 1122-1125, 2011
562011
Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies
B Vandevelde, C Okoro, M Gonzalez, B Swinnen, E Beyne
EuroSimE 2008-International Conference on Thermal, Mechanical and Multi …, 2008
562008
A zebrafish model for C9orf72 ALS reveals RNA toxicity as a pathogenic mechanism
B Swinnen, A Bento-Abreu, TF Gendron, S Boeynaems, E Bogaert, ...
Acta neuropathologica 135 (3), 427-443, 2018
542018
Implementation of an industry compliant, 5× 50μm, via-middle TSV technology on 300mm wafers
A Redolfi, D Velenis, S Thangaraju, P Nolmans, P Jaenen, M Kostermans, ...
2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 1384-1388, 2011
542011
3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
Y Civale, DS Tezcan, HGG Philipsen, FFC Duval, P Jaenen, Y Travaly, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 1 (6 …, 2011
472011
Analysis of the induced stresses in silicon during thermcompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture
C Okoro, M Gonzalez, B Vandevelde, B Swinnen, G Eneman, S Stoukatch, ...
2007 Proceedings 57th Electronic Components and Technology Conference, 249-255, 2007
462007
El sistema no puede realizar la operación en estos momentos. Inténtalo de nuevo más tarde.
Artículos 1–20