| Colonnade: A reconfigurable SRAM-based digital bit-serial compute-in-memory macro for processing neural networks H Kim, T Yoo, TTH Kim, B Kim IEEE Journal of Solid-State Circuits 56 (7), 2221-2233, 2021 | 83 | 2021 |
| A logic-compatible eDRAM compute-in-memory with embedded ADCs for processing neural networks C Yu, T Yoo, H Kim, TTH Kim, KCT Chuan, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 667-679, 2020 | 56 | 2020 |
| A 1-16b precision reconfigurable digital in-memory computing macro featuring column-MAC architecture and bit-serial computation H Kim, Q Chen, T Yoo, TTH Kim, B Kim ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 52 | 2019 |
| A 16K SRAM-based mixed-signal in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC H Kim, Q Chen, B Kim 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 35-36, 2019 | 40 | 2019 |
| 31.2 CIM-spin: A 0.5-to-1.2 V scalable annealing processor using digital compute-in-memory spin operators and register-based spins for combinatorial optimization problems Y Su, H Kim, B Kim 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 480-482, 2020 | 30 | 2020 |
| A logic compatible 4T dual embedded DRAM array for in-memory computation of deep neural networks T Yoo, H Kim, Q Chen, TTH Kim, B Kim 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 25 | 2019 |
| SRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks J Mu, H Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2412-2422, 2022 | 17 | 2022 |
| A scalable cmos ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems Y Su, J Mu, H Kim, B Kim IEEE Journal of Solid-State Circuits 57 (3), 858-868, 2022 | 17 | 2022 |
| A 1-16b reconfigurable 80kb 7t sram-based digital near-memory computing macro for processing neural networks H Kim, J Mu, C Yu, TTH Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1580-1590, 2023 | 15 | 2023 |
| A reconfigurable 16Kb AND8T SRAM macro with improved linearity for multibit compute-in memory of artificial intelligence edge devices V Sharma, JE Kim, H Kim, L Lu, TTH Kim IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 15 | 2022 |
| CIM-spin: A scalable CMOS annealing processor with digital in-memory spin operators and register spins for combinatorial optimization problems Y Su, H Kim, B Kim IEEE Journal of Solid-State Circuits 57 (7), 2263-2273, 2022 | 13 | 2022 |
| A 64 Kb reconfigurable full-precision digital ReRAM-based compute-in-memory for artificial intelligence applications V Sharma, H Kim, TTH Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3284-3296, 2022 | 12 | 2022 |
| BP-SCIM: A reconfigurable 8T SRAM macro for bit-parallel searching and computing in-memory Y Chen, J Mu, H Kim, L Lu, TTH Kim IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 5 | 2023 |
| A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory Y Chen, J Mu, H Kim, L Lu, TTH Kim 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2556-2560, 2022 | 3 | 2022 |
| A 252 spins scalable CMOS Ising chip featuring sparse and reconfigurable spin interconnects for combinatorial optimization problems Y Su, J Mu, H Kim, B Kim 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 3 | 2021 |
| A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks H Kim, Q Chen, T Yoo, TTH Kim, B Kim 2019 International SoC Design Conference (ISOCC), 166-167, 2019 | 3 | 2019 |
| A 16× 128 stochastic-binary processing element array for accelerating stochastic dot-product computation using 1-16 bit-stream length Q Chen, Y Su, H Kim, T Yoo, TTH Kim, B Kim 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 678-681, 2020 | 2 | 2020 |
| DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC YJ Jo, BP Yap, DH Yoon, H Kim, Y Zheng, TTH Kim 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 1 | 2023 |
| SRAM-Based Processing-in-Memory (PIM) H Kim, C Yu, B Kim Processing-in-Memory for AI: From Circuits to Systems, 41-63, 2022 | 1 | 2022 |
| The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results L Rota, F Mele, A Habib, H Kim, P King, B Markovic, AP Perez, A Dragone Journal of Instrumentation 19 (01), C01010, 2024 | | 2024 |
Bongjin KimUniversity of California, Santa BarbaraDirección de correo verificada de ucsb.edu
