| A scalable formal debugging approach with auto-correction capability based on static slicing and dynamic ranking for RTL datapath designs B Alizadeh, P Behnam, S Sadeghi-Kohan IEEE Transactions on Computers 64 (6), 1564-1578, 2014 | 17 | 2014 |
| Improving polynomial datapath debugging with HEDs S Sadeghi-Kohan, P Behnam, B Alizadeh, M Fujita, Z Navabi 2014 19th IEEE European Test Symposium (ETS), 1-6, 2014 | 7 | 2014 |
| Online self adjusting progressive age monitoring of timing variations S Sadeghi-Kohan, M Kamal, J McNeil, P Prinetto, Z Navabi 2015 10th International Conference on Design & Technology of Integrated …, 2015 | 6 | 2015 |
| Assertion based verification in TLM AA Ghofrani, F Javaheri, Z Navabi Design & Test Symposium (EWDTS), 2010 East-West, 509-513, 2010 | 5 | 2010 |
| An off-line MDSI interconnect BIST incorporated in BS 1149.1 M Mohammadi, S Sadeghi-Kohan, N Masoumi, Z Navabi 2014 19th IEEE European Test Symposium (ETS), 1-2, 2014 | 4 | 2014 |
| BS 1149.1 extensions for an online interconnect fault detection and recovery S Sadeghi-Kohan, M Namaki-Shoushtari, F Javaheri, Z Navabi 2012 IEEE International Test Conference, 1-9, 2012 | 4 | 2012 |
| Virtual tester development using HDL/PLI A Kamran, N Nemati, SS Kohan, Z Navabi 2010 East-West Design & Test Symposium (EWDTS), 412-415, 2010 | 4 | 2010 |
| Self-Adjusting Monitor for Measuring Aging Rate and Advancement S Sadeghi-Kohan, M Kamal, Z Navabi IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, TETCSI-2017-03-0092, 2018 | 3 | 2018 |
| Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation S Sadeghi-Kohan, A Kamran, F Forooghifar, Z Navabi 2015 10th International Conference on Design & Technology of Integrated …, 2015 | 3 | 2015 |
| A new structure for interconnect offline testing S Sadeghi-Kohan, S Keshavarz, F Zokaee, F Farahmandi, Z Navabi East-West Design & Test Symposium (EWDTS 2013), 1-5, 2013 | 2 | 2013 |
| Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects S Sadeghi-Kohan, S Hellebrand 2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020 | 1 | 2020 |
| Near-optimal node selection procedure for aging monitor placement S Sadeghi-Kohan, A Vafaei, Z Navabi 2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018 | 1 | 2018 |
| Performance and energy enhancement through an online single/multi level mode switching cache architecture R Rezaeizadeh Rookerd, S Sadeghi-Kohan, Z Navabi Proceedings of the 2018 on Great Lakes Symposium on VLSI, 33-38, 2018 | 1 | 2018 |
| Variation-Aware Test for Logic Interconnects using Neural Networks–A Case Study A Sprenger, S Sadeghi-Kohan, JD Reimer, S Hellebrand 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020 | | 2020 |
| Universal mitigation of NBTI-induced aging by design randomization M Jenihhin, A Kamkin, Z Navabi, S Sadeghi-Kohan 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-5, 2016 | | 2016 |
| Multi Level Test Package A package for C/C++ gate level fault simulation of system level design SS Kohan, F Javaheri, S Mahmoodi, Z Navabi Journal of Shanghai Normal University (Natural Sciences), 05, 2010 | | 2010 |
| Special Section on Reliability-awaRe DeSign anD analySiS MethoDS foR Digital SySteMS: fRoM gate to SySteM level A Miele, Q Yu, MK Michael, A Sari, M Psarakis, KN Dang, AB Ahmed, ... | | |
Zainalabedin NavabiProfessor of Electrical and Computer Engineering, University of TehranDirección de correo verificada de ut.ac.ir
