Ghasem Pasandi
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Año
An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs
G Pasandi, SM Fakhraie
IEEE Transactions on Electron Devices 61 (7), 2357- 2363, 2014
602014
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
G Pasandi, SM Fakhraie
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015
442015
A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS
G Pasandi, SM Fakhraie
2013 21st Iranian Conference on Electrical Engineering (ICEE), 1-6, 2013
322013
A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS
G Pasandi, SM Fakhraie
2013 21st Iranian Conference on Electrical Engineering (ICEE), 1-6, 2013
322013
PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits
G Pasandi, M Pedram
IEEE Transactions on Applied Superconductivity 29 (4), 2018
172018
SFQmap: A technology mapping tool for single flux quantum logic circuits
G Pasandi, A Shafaei, M Pedram
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
152018
A new low-power 10T SRAM cell with improved read SNM
G Pasandi, M Jafari, M Imani
International Journal of Electronics 102 (10), 1621-1633, 2015
112015
Nullanet: Training deep neural networks for reduced-memory-access inference
M Nazemi, G Pasandi, M Pedram
arXiv preprint arXiv:1807.08716, 2018
102018
Sport lab sfq logic circuit benchmark suite
N Katam, SN Shahsavani, TR Lin, G Pasandi, A Shafaei, M Pedram
Univ. South. California, Los Angeles, CA, USA, Tech. Rep, 2017
102017
Energy-efficient, low-latency realization of neural networks through boolean logic minimization
M Nazemi, G Pasandi, M Pedram
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
82019
A new sub-300mv 8T SRAM cell design in 90nm CMOS
G Pasandi, SM Fakhraie
The 17th CSI International Symposium on Computer Architecture & Digital …, 2013
82013
A new low-leakage T-Gate based 8T SRAM cell with improved write-ability in 90nm CMOS technology
G Pasandi, E Qasemi, SM Fakhraie
2014 22nd Iranian Conference on Electrical Engineering (ICEE), 382-386, 2014
72014
A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization.
G Pasandi, M Pedram
ICCAD, 1-8, 2019
62019
Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs
G Pasandi, M Pedram
IET Circuits, Devices & Systems 12 (4), 460-466, 2018
62018
Balanced factorization and rewriting algorithms for synthesizing single flux quantum logic circuits
G Pasandi, M Pedram
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 183-188, 2019
52019
A graph partitioning algorithm with application in synthesizing single flux quantum logic circuits
G Pasandi, M Pedram
arXiv preprint arXiv:1810.00134, 2018
52018
An Efficient Pipelined Architecture for Superconducting Single Flux Quantum Logic Circuits Utilizing Dual Clocks
G Pasandi, M Pedram
IEEE Transactions on Applied Superconductivity 30 (2), 1-12, 2019
32019
Approximate logic synthesis: A reinforcement learning-based technology mapping approach
G Pasandi, S Nazarian, M Pedram
20th International Symposium on Quality Electronic Design (ISQED), 26-32, 2019
32019
A new low-power SRAM block suitable for applications with normal data distribution
G Pasandi, K Mehrabi, SM Fakhraie
2015 23rd Iranian Conference on Electrical Engineering, 1316-1321, 2015
32015
Deep-PowerX: A deep learning-based framework for low-power approximate logic synthesis
G Pasandi, M Peterson, M Herrera, S Nazarian, M Pedram
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
12020
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