Nanomaterials, nanotechnologies and design: an introduction for engineers and architects DL Schodek, P Ferreira, MF Ashby
Butterworth-Heinemann, 2009
545 2009 Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ...
2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010
311 2010 Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain S Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 2016
117 2016 Informatics for materials science and engineering: data-driven discovery for accelerated experimentation and application K Rajan
Butterworth-Heinemann, 2013
106 2013 Mechanisms of porous dielectric film modification induced by reducing and oxidizing ash plasmas N Posseme, T Chevolleau, T David, M Darnon, O Louveau, O Joubert
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2007
103 2007 First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers L Brunet, P Batude, C Fenouillet-Béranger, P Besombes, L Hortemel, ...
2016 IEEE symposium on VLSI technology, 1-2, 2016
96 2016 Etching mechanisms of low-k SiOCH and selectivity to SiCH and in fluorocarbon based plasmas N Posseme, T Chevolleau, O Joubert, L Vallier, P Mangiagalli
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2003
77 2003 Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011
73 2011 Alternative process for thin layer etching: Application to nitride spacer etching stopping on silicon germanium N Posseme, O Pollet, S Barnola
Applied Physics Letters 105 (5), 2014
65 2014 Etching of porous SiOCH materials in fluorocarbon-based plasmas N Posseme, T Chevolleau, O Joubert, L Vallier, N Rochat
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2004
63 2004 Method for vibration damping using superelastic alloys Y Sherwin, DG Ulmer
US Patent 6,796,408, 2004
49 2004 Thin layer etching of silicon nitride: A comprehensive study of selective removal using NH3/NF3 remote plasma N Posseme, V Ah-Leung, O Pollet, C Arvet, M Garcia-Barros
Journal of Vacuum Science & Technology A 34 (6), 2016
47 2016 Electrochemical biosensors S Cosnier
CRC Press, 2015
44 2015 Plasma deposition—Impact of ions in plasma enhanced chemical vapor deposition, plasma enhanced atomic layer deposition, and applications to area selective deposition C Vallée, M Bonvalot, S Belahcen, T Yeghoyan, M Jaffal, R Vallat, ...
Journal of Vacuum Science & Technology A 38 (3), 2020
41 2020 Method of forming spacers for a gate of a transistor N Posseme
US Patent App. 14/797,345, 2016
41 2016 Patterning of narrow porous SiOCH trenches using a TiN hard mask M Darnon, T Chevolleau, D Eon, R Bouyssou, B Pelissier, L Vallier, ...
Microelectronic engineering 85 (11), 2226-2235, 2008
41 2008 Impact of low-k structure and porosity on etch processes M Darnon, N Casiez, T Chevolleau, G Dubois, W Volksen, TJ Frot, ...
Journal of Vacuum Science & Technology B 31 (1), 2013
31 2013 Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low-k dielectric material M Aimadeddine, V Arnal, A Farcy, C Guedj, T Chevolleau, N Possémé, ...
Microelectronic Engineering 82 (3-4), 341-347, 2005
31 2005 Roughening of porous SiCOH materials in fluorocarbon plasmas F Bailly, T David, T Chevolleau, M Darnon, N Posseme, R Bouyssou, ...
Journal of Applied Physics 108 (1), 2010
30 2010 Methods of forming silicon nitride spacers N Posseme, O Joubert, T David, T Lill
US Patent 9,257,293, 2016
29 2016